Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.50	98.25	93.97	97.02	93.60	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.42	99.92	92.75	82.54	93.60	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T17,T26,T30

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T20
1	0	Covered	T5,T34,T7

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T9	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T6,T40,T41	Yes	T6,T40,T41	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
edn_i[1].edn_req	Yes	Yes	T2,T42,T43	Yes	T2,T42,T43	INPUT
edn_i[2].edn_req	Yes	Yes	T2,T3,T42	Yes	T2,T3,T42	INPUT
edn_i[3].edn_req	Yes	Yes	T42,T10,T44	Yes	T42,T10,T44	INPUT
edn_i[4].edn_req	Yes	Yes	T3,T5,T10	Yes	T3,T5,T10	INPUT
edn_i[5].edn_req	Yes	Yes	T17,T42,T10	Yes	T17,T42,T10	INPUT
edn_i[6].edn_req	Yes	Yes	T17,T25,T42	Yes	T17,T25,T42	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T9,T4	Yes	T1,T2,T9	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T9,T4,T6	Yes	T2,T9,T4	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T42,T43,T45	Yes	T2,T42,T43	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T42,T43,T45	Yes	T42,T43,T45	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T2,T42,T43	Yes	T2,T42,T43	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T2,T3,T42	Yes	T2,T3,T42	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T2,T3,T42	Yes	T2,T3,T42	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T2,T3,T42	Yes	T2,T3,T42	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T42,T10,T44	Yes	T42,T10,T44	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T42,T23,T46	Yes	T42,T10,T44	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T42,T10,T44	Yes	T42,T10,T44	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T3,T10,T43	Yes	T3,T10,T43	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T10,T43,T45	Yes	T3,T10,T43	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T3,T10,T43	Yes	T3,T10,T43	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T17,T42,T10	Yes	T17,T42,T10	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T17,T34,T11	Yes	T17,T42,T10	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T17,T42,T10	Yes	T17,T42,T10	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T17,T25,T42	Yes	T17,T25,T42	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T45,T47,T48	Yes	T42,T43,T45	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T17,T25,T42	Yes	T17,T25,T42	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T2,T3,T9	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T17,T14,T49	Yes	T17,T14,T49	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T17,T26,T30	Yes	T17,T26,T30	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T5,T34,T7	Yes	T5,T34,T7	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T17,T26,T30	Yes	T17,T26,T30	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T5,T34,T7	Yes	T5,T34,T7	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T6,T50	Yes	T4,T6,T50	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T6,T50	Yes	T4,T6,T50	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	211957676	211769051	0	0
CsrngAppIfOut_A	211957676	211769051	0	0
FpvSecCmCntAlertCheck_A	211957676	124	0	0
FpvSecCmGenCmdFifoRptrCheck_A	211957676	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	211957676	80	0	0
FpvSecCmMainFsmCheck_A	211957676	80	0	0
FpvSecCmRegWeOnehotCheck_A	211957676	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	211957676	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	211957676	80	0	0
IntrEdnCmdReqDoneKnownO_A	211957676	211769051	0	0
TlAReadyKnownO_A	211957676	211769051	0	0
TlDValidKnownO_A	211957676	211769051	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	211957676	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	211957676	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	211957676	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	211957676	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	211957676	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	211957676	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	211957676	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	211957676	636002	0	314
gen_edn_if_asserts[0].EdnDataStable_A	211957676	68405	0	436
gen_edn_if_asserts[0].EdnEndPointOut_A	211957676	211769051	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	211957676	147365	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	211957676	636002	0	314
gen_edn_if_asserts[1].EdnDataStable_A	211957676	5693	0	132
gen_edn_if_asserts[1].EdnEndPointOut_A	211957676	211769051	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	211957676	147365	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	211957676	636002	0	314
gen_edn_if_asserts[2].EdnDataStable_A	211957676	4155	0	117
gen_edn_if_asserts[2].EdnEndPointOut_A	211957676	211769051	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	211957676	147365	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	211957676	636002	0	314
gen_edn_if_asserts[3].EdnDataStable_A	211957676	1894	0	108
gen_edn_if_asserts[3].EdnEndPointOut_A	211957676	211769051	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	211957676	147365	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	211957676	636002	0	314
gen_edn_if_asserts[4].EdnDataStable_A	211957676	4632	0	114
gen_edn_if_asserts[4].EdnEndPointOut_A	211957676	211769051	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	211957676	147365	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	211957676	636002	0	314
gen_edn_if_asserts[5].EdnDataStable_A	211957676	3842	0	98
gen_edn_if_asserts[5].EdnEndPointOut_A	211957676	211769051	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	211957676	147365	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	211957676	636002	0	314
gen_edn_if_asserts[6].EdnDataStable_A	211957676	2507	0	94
gen_edn_if_asserts[6].EdnEndPointOut_A	211957676	211769051	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	211957676	147365	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	211769051	0	0
T1	1018	950	0	0
T2	2582	2515	0	0
T3	2731	2646	0	0
T4	32835	32105	0	0
T5	1184	1026	0	0
T6	456502	456487	0	0
T9	4997	4933	0	0
T17	2015	1960	0	0
T25	1296	1196	0	0
T26	1959	1890	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	211769051	0	0
T1	1018	950	0	0
T2	2582	2515	0	0
T3	2731	2646	0	0
T4	32835	32105	0	0
T5	1184	1026	0	0
T6	456502	456487	0	0
T9	4997	4933	0	0
T17	2015	1960	0	0
T25	1296	1196	0	0
T26	1959	1890	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	124	0	0
T8	1473	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T23	2439	0	0	0
T24	6215	0	0	0
T31	2040	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	2725	0	0	0
T59	2170	0	0	0
T60	1947	0	0	0
T61	1488	0	0	0
T62	1666	0	0	0
T63	4832	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	80	0	0
T18	24579	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	18050	0	0	0
T67	2770	0	0	0
T68	577	0	0	0
T69	1264	0	0	0
T70	2736	0	0	0
T71	2360	0	0	0
T72	1819	0	0	0
T73	1685	0	0	0
T74	1143	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	80	0	0
T18	24579	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	18050	0	0	0
T67	2770	0	0	0
T68	577	0	0	0
T69	1264	0	0	0
T70	2736	0	0	0
T71	2360	0	0	0
T72	1819	0	0	0
T73	1685	0	0	0
T74	1143	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	80	0	0
T18	24579	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	18050	0	0	0
T67	2770	0	0	0
T68	577	0	0	0
T69	1264	0	0	0
T70	2736	0	0	0
T71	2360	0	0	0
T72	1819	0	0	0
T73	1685	0	0	0
T74	1143	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	80	0	0
T18	24579	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	18050	0	0	0
T67	2770	0	0	0
T68	577	0	0	0
T69	1264	0	0	0
T70	2736	0	0	0
T71	2360	0	0	0
T72	1819	0	0	0
T73	1685	0	0	0
T74	1143	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	80	0	0
T18	24579	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	18050	0	0	0
T67	2770	0	0	0
T68	577	0	0	0
T69	1264	0	0	0
T70	2736	0	0	0
T71	2360	0	0	0
T72	1819	0	0	0
T73	1685	0	0	0
T74	1143	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	80	0	0
T18	24579	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	18050	0	0	0
T67	2770	0	0	0
T68	577	0	0	0
T69	1264	0	0	0
T70	2736	0	0	0
T71	2360	0	0	0
T72	1819	0	0	0
T73	1685	0	0	0
T74	1143	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	211769051	0	0
T1	1018	950	0	0
T2	2582	2515	0	0
T3	2731	2646	0	0
T4	32835	32105	0	0
T5	1184	1026	0	0
T6	456502	456487	0	0
T9	4997	4933	0	0
T17	2015	1960	0	0
T25	1296	1196	0	0
T26	1959	1890	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	211769051	0	0
T1	1018	950	0	0
T2	2582	2515	0	0
T3	2731	2646	0	0
T4	32835	32105	0	0
T5	1184	1026	0	0
T6	456502	456487	0	0
T9	4997	4933	0	0
T17	2015	1960	0	0
T25	1296	1196	0	0
T26	1959	1890	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	211769051	0	0
T1	1018	950	0	0
T2	2582	2515	0	0
T3	2731	2646	0	0
T4	32835	32105	0	0
T5	1184	1026	0	0
T6	456502	456487	0	0
T9	4997	4933	0	0
T17	2015	1960	0	0
T25	1296	1196	0	0
T26	1959	1890	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	80	0	0
T18	24579	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	18050	0	0	0
T67	2770	0	0	0
T68	577	0	0	0
T69	1264	0	0	0
T70	2736	0	0	0
T71	2360	0	0	0
T72	1819	0	0	0
T73	1685	0	0	0
T74	1143	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	80	0	0
T18	24579	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	18050	0	0	0
T67	2770	0	0	0
T68	577	0	0	0
T69	1264	0	0	0
T70	2736	0	0	0
T71	2360	0	0	0
T72	1819	0	0	0
T73	1685	0	0	0
T74	1143	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	80	0	0
T18	24579	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	18050	0	0	0
T67	2770	0	0	0
T68	577	0	0	0
T69	1264	0	0	0
T70	2736	0	0	0
T71	2360	0	0	0
T72	1819	0	0	0
T73	1685	0	0	0
T74	1143	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	80	0	0
T18	24579	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	18050	0	0	0
T67	2770	0	0	0
T68	577	0	0	0
T69	1264	0	0	0
T70	2736	0	0	0
T71	2360	0	0	0
T72	1819	0	0	0
T73	1685	0	0	0
T74	1143	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	80	0	0
T18	24579	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	18050	0	0	0
T67	2770	0	0	0
T68	577	0	0	0
T69	1264	0	0	0
T70	2736	0	0	0
T71	2360	0	0	0
T72	1819	0	0	0
T73	1685	0	0	0
T74	1143	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	80	0	0
T18	24579	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	18050	0	0	0
T67	2770	0	0	0
T68	577	0	0	0
T69	1264	0	0	0
T70	2736	0	0	0
T71	2360	0	0	0
T72	1819	0	0	0
T73	1685	0	0	0
T74	1143	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	80	0	0
T18	24579	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	18050	0	0	0
T67	2770	0	0	0
T68	577	0	0	0
T69	1264	0	0	0
T70	2736	0	0	0
T71	2360	0	0	0
T72	1819	0	0	0
T73	1685	0	0	0
T74	1143	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	636002	0	314
T1	1018	12	0	0
T2	2582	14	0	0
T3	2731	22	0	0
T4	32835	2806	0	0
T5	1184	733	0	0
T6	456502	2887	0	2
T9	4997	202	0	0
T17	2015	223	0	0
T21	0	0	0	2
T25	1296	140	0	0
T26	1959	131	0	0
T40	0	0	0	2
T41	0	0	0	2
T60	0	0	0	2
T63	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	68405	0	436
T1	1018	3	0	1
T2	2582	3	0	1
T3	2731	0	0	0
T4	32835	16	0	0
T5	1184	0	0	0
T6	456502	120	0	0
T9	4997	628	0	1
T10	0	0	0	1
T14	0	0	0	1
T17	2015	0	0	0
T25	1296	0	0	0
T26	1959	8	0	1
T30	0	4	0	1
T42	0	3	0	1
T49	0	0	0	1
T50	0	10	0	0
T79	0	4	0	0
T80	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	211769051	0	0
T1	1018	950	0	0
T2	2582	2515	0	0
T3	2731	2646	0	0
T4	32835	32105	0	0
T5	1184	1026	0	0
T6	456502	456487	0	0
T9	4997	4933	0	0
T17	2015	1960	0	0
T25	1296	1196	0	0
T26	1959	1890	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	147365	0	0
T5	1184	284	0	0
T6	456502	0	0	0
T7	0	338	0	0
T8	0	405	0	0
T10	3184	0	0	0
T15	0	629	0	0
T16	0	1152	0	0
T26	1959	0	0	0
T30	2518	0	0	0
T31	0	20	0	0
T34	0	24	0	0
T42	2197	0	0	0
T50	18016	0	0	0
T51	0	397	0	0
T75	8148	0	0	0
T79	919	0	0	0
T80	1679	0	0	0
T81	0	612	0	0
T82	0	290	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	636002	0	314
T1	1018	12	0	0
T2	2582	14	0	0
T3	2731	22	0	0
T4	32835	2806	0	0
T5	1184	733	0	0
T6	456502	2887	0	2
T9	4997	202	0	0
T17	2015	223	0	0
T21	0	0	0	2
T25	1296	140	0	0
T26	1959	131	0	0
T40	0	0	0	2
T41	0	0	0	2
T60	0	0	0	2
T63	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	5693	0	132
T2	2582	3	0	1
T3	2731	0	0	0
T4	32835	0	0	0
T5	1184	0	0	0
T6	456502	0	0	0
T7	0	1	0	0
T9	4997	0	0	0
T11	0	3	0	1
T12	0	0	0	1
T17	2015	0	0	0
T25	1296	0	0	0
T26	1959	0	0	0
T42	0	11	0	1
T43	0	17	0	1
T45	0	53	0	1
T46	0	25	0	1
T79	919	0	0	0
T83	0	43	0	1
T84	0	4	0	0
T85	0	4	0	1
T86	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	211769051	0	0
T1	1018	950	0	0
T2	2582	2515	0	0
T3	2731	2646	0	0
T4	32835	32105	0	0
T5	1184	1026	0	0
T6	456502	456487	0	0
T9	4997	4933	0	0
T17	2015	1960	0	0
T25	1296	1196	0	0
T26	1959	1890	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	147365	0	0
T5	1184	284	0	0
T6	456502	0	0	0
T7	0	338	0	0
T8	0	405	0	0
T10	3184	0	0	0
T15	0	629	0	0
T16	0	1152	0	0
T26	1959	0	0	0
T30	2518	0	0	0
T31	0	20	0	0
T34	0	24	0	0
T42	2197	0	0	0
T50	18016	0	0	0
T51	0	397	0	0
T75	8148	0	0	0
T79	919	0	0	0
T80	1679	0	0	0
T81	0	612	0	0
T82	0	290	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	636002	0	314
T1	1018	12	0	0
T2	2582	14	0	0
T3	2731	22	0	0
T4	32835	2806	0	0
T5	1184	733	0	0
T6	456502	2887	0	2
T9	4997	202	0	0
T17	2015	223	0	0
T21	0	0	0	2
T25	1296	140	0	0
T26	1959	131	0	0
T40	0	0	0	2
T41	0	0	0	2
T60	0	0	0	2
T63	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	4155	0	117
T2	2582	28	0	1
T3	2731	36	0	1
T4	32835	0	0	0
T5	1184	0	0	0
T6	456502	0	0	0
T8	0	1	0	0
T9	4997	0	0	0
T11	0	0	0	1
T17	2015	0	0	0
T23	0	3	0	1
T25	1296	0	0	0
T26	1959	0	0	0
T42	0	49	0	1
T44	0	65	0	1
T45	0	18	0	1
T46	0	46	0	1
T47	0	3	0	1
T79	919	0	0	0
T87	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	211769051	0	0
T1	1018	950	0	0
T2	2582	2515	0	0
T3	2731	2646	0	0
T4	32835	32105	0	0
T5	1184	1026	0	0
T6	456502	456487	0	0
T9	4997	4933	0	0
T17	2015	1960	0	0
T25	1296	1196	0	0
T26	1959	1890	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	147365	0	0
T5	1184	284	0	0
T6	456502	0	0	0
T7	0	338	0	0
T8	0	405	0	0
T10	3184	0	0	0
T15	0	629	0	0
T16	0	1152	0	0
T26	1959	0	0	0
T30	2518	0	0	0
T31	0	20	0	0
T34	0	24	0	0
T42	2197	0	0	0
T50	18016	0	0	0
T51	0	397	0	0
T75	8148	0	0	0
T79	919	0	0	0
T80	1679	0	0	0
T81	0	612	0	0
T82	0	290	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	636002	0	314
T1	1018	12	0	0
T2	2582	14	0	0
T3	2731	22	0	0
T4	32835	2806	0	0
T5	1184	733	0	0
T6	456502	2887	0	2
T9	4997	202	0	0
T17	2015	223	0	0
T21	0	0	0	2
T25	1296	140	0	0
T26	1959	131	0	0
T40	0	0	0	2
T41	0	0	0	2
T60	0	0	0	2
T63	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	1894	0	108
T10	3184	31	0	1
T11	0	27	0	1
T12	0	26	0	1
T14	2391	0	0	0
T23	0	28	0	1
T30	2518	0	0	0
T34	857	0	0	0
T42	2197	45	0	1
T43	1647	0	0	0
T44	3336	3	0	1
T45	0	3	0	1
T46	0	9	0	1
T49	2534	0	0	0
T75	8148	0	0	0
T80	1679	0	0	0
T88	0	4	0	0
T89	0	53	0	1
T90	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	211769051	0	0
T1	1018	950	0	0
T2	2582	2515	0	0
T3	2731	2646	0	0
T4	32835	32105	0	0
T5	1184	1026	0	0
T6	456502	456487	0	0
T9	4997	4933	0	0
T17	2015	1960	0	0
T25	1296	1196	0	0
T26	1959	1890	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	147365	0	0
T5	1184	284	0	0
T6	456502	0	0	0
T7	0	338	0	0
T8	0	405	0	0
T10	3184	0	0	0
T15	0	629	0	0
T16	0	1152	0	0
T26	1959	0	0	0
T30	2518	0	0	0
T31	0	20	0	0
T34	0	24	0	0
T42	2197	0	0	0
T50	18016	0	0	0
T51	0	397	0	0
T75	8148	0	0	0
T79	919	0	0	0
T80	1679	0	0	0
T81	0	612	0	0
T82	0	290	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	636002	0	314
T1	1018	12	0	0
T2	2582	14	0	0
T3	2731	22	0	0
T4	32835	2806	0	0
T5	1184	733	0	0
T6	456502	2887	0	2
T9	4997	202	0	0
T17	2015	223	0	0
T21	0	0	0	2
T25	1296	140	0	0
T26	1959	131	0	0
T40	0	0	0	2
T41	0	0	0	2
T60	0	0	0	2
T63	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	4632	0	114
T3	2731	3	0	1
T4	32835	0	0	0
T5	1184	0	0	0
T6	456502	0	0	0
T9	4997	0	0	0
T10	0	36	0	1
T17	2015	0	0	0
T21	0	4	0	0
T23	0	85	0	1
T24	0	0	0	1
T25	1296	0	0	0
T26	1959	0	0	0
T43	0	63	0	1
T45	0	8	0	1
T47	0	60	0	1
T50	18016	0	0	0
T62	0	4	0	1
T79	919	0	0	0
T83	0	53	0	1
T91	0	3	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	211769051	0	0
T1	1018	950	0	0
T2	2582	2515	0	0
T3	2731	2646	0	0
T4	32835	32105	0	0
T5	1184	1026	0	0
T6	456502	456487	0	0
T9	4997	4933	0	0
T17	2015	1960	0	0
T25	1296	1196	0	0
T26	1959	1890	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	147365	0	0
T5	1184	284	0	0
T6	456502	0	0	0
T7	0	338	0	0
T8	0	405	0	0
T10	3184	0	0	0
T15	0	629	0	0
T16	0	1152	0	0
T26	1959	0	0	0
T30	2518	0	0	0
T31	0	20	0	0
T34	0	24	0	0
T42	2197	0	0	0
T50	18016	0	0	0
T51	0	397	0	0
T75	8148	0	0	0
T79	919	0	0	0
T80	1679	0	0	0
T81	0	612	0	0
T82	0	290	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	636002	0	314
T1	1018	12	0	0
T2	2582	14	0	0
T3	2731	22	0	0
T4	32835	2806	0	0
T5	1184	733	0	0
T6	456502	2887	0	2
T9	4997	202	0	0
T17	2015	223	0	0
T21	0	0	0	2
T25	1296	140	0	0
T26	1959	131	0	0
T40	0	0	0	2
T41	0	0	0	2
T60	0	0	0	2
T63	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	3842	0	98
T4	32835	0	0	0
T5	1184	0	0	0
T6	456502	0	0	0
T10	0	3	0	1
T11	0	52	0	1
T12	0	0	0	1
T17	2015	4	0	0
T24	0	3	0	1
T25	1296	0	0	0
T26	1959	0	0	0
T30	2518	0	0	0
T34	0	1	0	0
T42	2197	3	0	1
T45	0	3	0	1
T46	0	3	0	1
T50	18016	0	0	0
T76	0	4	0	0
T79	919	0	0	0
T86	0	0	0	1
T92	0	4	0	1
T93	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	211769051	0	0
T1	1018	950	0	0
T2	2582	2515	0	0
T3	2731	2646	0	0
T4	32835	32105	0	0
T5	1184	1026	0	0
T6	456502	456487	0	0
T9	4997	4933	0	0
T17	2015	1960	0	0
T25	1296	1196	0	0
T26	1959	1890	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	147365	0	0
T5	1184	284	0	0
T6	456502	0	0	0
T7	0	338	0	0
T8	0	405	0	0
T10	3184	0	0	0
T15	0	629	0	0
T16	0	1152	0	0
T26	1959	0	0	0
T30	2518	0	0	0
T31	0	20	0	0
T34	0	24	0	0
T42	2197	0	0	0
T50	18016	0	0	0
T51	0	397	0	0
T75	8148	0	0	0
T79	919	0	0	0
T80	1679	0	0	0
T81	0	612	0	0
T82	0	290	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	636002	0	314
T1	1018	12	0	0
T2	2582	14	0	0
T3	2731	22	0	0
T4	32835	2806	0	0
T5	1184	733	0	0
T6	456502	2887	0	2
T9	4997	202	0	0
T17	2015	223	0	0
T21	0	0	0	2
T25	1296	140	0	0
T26	1959	131	0	0
T40	0	0	0	2
T41	0	0	0	2
T60	0	0	0	2
T63	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	2507	0	94
T4	32835	0	0	0
T5	1184	0	0	0
T6	456502	0	0	0
T11	0	3	0	1
T17	2015	4	0	1
T25	1296	3	0	1
T26	1959	0	0	0
T30	2518	0	0	0
T42	2197	3	0	1
T43	0	20	0	1
T45	0	53	0	1
T46	0	3	0	1
T47	0	4	0	1
T50	18016	0	0	0
T78	0	4	0	0
T79	919	0	0	0
T94	0	4	0	0
T95	0	0	0	1
T96	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	211769051	0	0
T1	1018	950	0	0
T2	2582	2515	0	0
T3	2731	2646	0	0
T4	32835	32105	0	0
T5	1184	1026	0	0
T6	456502	456487	0	0
T9	4997	4933	0	0
T17	2015	1960	0	0
T25	1296	1196	0	0
T26	1959	1890	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211957676	147365	0	0
T5	1184	284	0	0
T6	456502	0	0	0
T7	0	338	0	0
T8	0	405	0	0
T10	3184	0	0	0
T15	0	629	0	0
T16	0	1152	0	0
T26	1959	0	0	0
T30	2518	0	0	0
T31	0	20	0	0
T34	0	24	0	0
T42	2197	0	0	0
T50	18016	0	0	0
T51	0	397	0	0
T75	8148	0	0	0
T79	919	0	0	0
T80	1679	0	0	0
T81	0	612	0	0
T82	0	290	0	0