Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	212534060	9113030	0	0
boot_gen_cmd_rd_A	212534060	65784	0	0
boot_ins_cmd_rd_A	212534060	74720	0	0
ctrl_rd_A	212534060	65592	0	0
err_code_test_rd_A	212534060	75744	0	0
intr_enable_rd_A	212534060	72353	0	0
max_num_reqs_between_reseeds_rd_A	212534060	66165	0	0
regwen_rd_A	212534060	74632	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212534060	9113030	0	0
T6	456502	155150	0	0
T10	3184	0	0	0
T14	2391	0	0	0
T30	2518	0	0	0
T34	857	0	0	0
T40	0	325545	0	0
T41	0	149397	0	0
T42	2197	0	0	0
T50	18016	0	0	0
T75	8148	0	0	0
T77	0	324373	0	0
T79	919	0	0	0
T80	1679	0	0	0
T108	0	62799	0	0
T226	0	48665	0	0
T227	0	142942	0	0
T228	0	127865	0	0
T229	0	175738	0	0
T230	0	166598	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212534060	65784	0	0
T6	456502	4285	0	0
T10	3184	0	0	0
T14	2391	0	0	0
T30	2518	0	0	0
T34	857	0	0	0
T40	0	9756	0	0
T42	2197	0	0	0
T50	18016	0	0	0
T75	8148	0	0	0
T79	919	0	0	0
T80	1679	0	0	0
T226	0	1481	0	0
T228	0	3806	0	0
T231	0	5526	0	0
T232	0	2232	0	0
T233	0	5259	0	0
T234	0	3252	0	0
T235	0	2739	0	0
T236	0	3686	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212534060	74720	0	0
T6	456502	4903	0	0
T10	3184	0	0	0
T14	2391	0	0	0
T30	2518	0	0	0
T34	857	0	0	0
T40	0	11238	0	0
T42	2197	0	0	0
T50	18016	0	0	0
T75	8148	0	0	0
T79	919	0	0	0
T80	1679	0	0	0
T226	0	1546	0	0
T228	0	4691	0	0
T231	0	5992	0	0
T232	0	2575	0	0
T233	0	6104	0	0
T234	0	3710	0	0
T235	0	3278	0	0
T236	0	4321	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212534060	65592	0	0
T6	456502	4377	0	0
T10	3184	0	0	0
T14	2391	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T30	2518	0	0	0
T34	857	0	0	0
T40	0	9153	0	0
T42	2197	0	0	0
T50	18016	0	0	0
T75	8148	0	0	0
T79	919	0	0	0
T80	1679	0	0	0
T104	0	1	0	0
T168	0	2	0	0
T226	0	1455	0	0
T228	0	3760	0	0
T231	0	5174	0	0
T237	0	1	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212534060	75744	0	0
T6	456502	5056	0	0
T10	3184	0	0	0
T14	2391	0	0	0
T30	2518	0	0	0
T34	857	0	0	0
T40	0	11314	0	0
T42	2197	0	0	0
T50	18016	0	0	0
T75	8148	0	0	0
T79	919	0	0	0
T80	1679	0	0	0
T226	0	1806	0	0
T228	0	4809	0	0
T231	0	5900	0	0
T232	0	2616	0	0
T233	0	5902	0	0
T234	0	3775	0	0
T235	0	3566	0	0
T236	0	4194	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212534060	72353	0	0
T4	32835	38	0	0
T5	1184	0	0	0
T6	456502	4831	0	0
T26	1959	0	0	0
T30	2518	0	0	0
T40	0	10280	0	0
T42	2197	0	0	0
T50	18016	47	0	0
T75	8148	0	0	0
T79	919	0	0	0
T80	1679	0	0	0
T226	0	1561	0	0
T228	0	4690	0	0
T231	0	5619	0	0
T232	0	2619	0	0
T238	0	9	0	0
T239	0	15	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212534060	66165	0	0
T6	456502	4259	0	0
T10	3184	0	0	0
T14	2391	0	0	0
T30	2518	0	0	0
T34	857	0	0	0
T40	0	9794	0	0
T42	2197	0	0	0
T50	18016	0	0	0
T75	8148	0	0	0
T79	919	0	0	0
T80	1679	0	0	0
T226	0	1426	0	0
T228	0	3769	0	0
T231	0	5366	0	0
T232	0	2280	0	0
T233	0	5186	0	0
T234	0	3463	0	0
T235	0	2882	0	0
T236	0	3561	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212534060	74632	0	0
T6	456502	5042	0	0
T10	3184	0	0	0
T14	2391	0	0	0
T30	2518	0	0	0
T34	857	0	0	0
T40	0	11145	0	0
T42	2197	0	0	0
T50	18016	0	0	0
T75	8148	0	0	0
T79	919	0	0	0
T80	1679	0	0	0
T226	0	1683	0	0
T228	0	4174	0	0
T231	0	5955	0	0
T232	0	2499	0	0
T233	0	5876	0	0
T234	0	3757	0	0
T235	0	3369	0	0
T236	0	3905	0	0