Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.17	98.25	93.97	91.35	91.28	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	88.51	99.92	92.75	49.41	91.28	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T23

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T19
1	0	Covered	T4,T6,T33

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T22,T24	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T10,T26	Yes	T2,T10,T26	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T2,T3,T22	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T3,T22	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T23,T24,T11	Yes	T23,T24,T11	INPUT
edn_i[2].edn_req	Yes	Yes	T24,T43,T44	Yes	T24,T43,T44	INPUT
edn_i[3].edn_req	Yes	Yes	T10,T45,T21	Yes	T10,T45,T21	INPUT
edn_i[4].edn_req	Yes	Yes	T24,T46,T45	Yes	T24,T46,T45	INPUT
edn_i[5].edn_req	Yes	Yes	T47,T33,T48	Yes	T47,T33,T48	INPUT
edn_i[6].edn_req	Yes	Yes	T24,T47,T44	Yes	T24,T47,T44	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T4,T15	Yes	T2,T3,T4	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T23,T24,T11	Yes	T23,T24,T11	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T24,T11,T49	Yes	T24,T11,T15	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T23,T24,T11	Yes	T23,T24,T11	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T43,T44,T50	Yes	T43,T44,T50	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T44,T34,T51	Yes	T43,T44,T50	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T24,T43,T44	Yes	T24,T43,T44	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T10,T45,T21	Yes	T10,T45,T21	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T52,T44,T53	Yes	T10,T47,T52	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T10,T45,T21	Yes	T10,T45,T21	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T24,T45,T44	Yes	T24,T46,T45	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T24,T44,T54	Yes	T24,T46,T44	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T24,T46,T45	Yes	T24,T46,T45	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T47,T48,T44	Yes	T47,T48,T44	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T48,T55,T56	Yes	T48,T44,T12	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T47,T33,T48	Yes	T47,T33,T48	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T24,T47,T44	Yes	T24,T47,T44	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T44,T53,T57	Yes	T24,T44,T53	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T24,T47,T44	Yes	T24,T47,T44	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T24,T11	Yes	T1,T24,T11	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T24,T11	Yes	T2,T3,T24	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T2,T10,T58	Yes	T2,T10,T58	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T22,T25,T4	Yes	T22,T25,T4	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T22,T25,T4	Yes	T22,T25,T4	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T5,T40,T41	Yes	T5,T40,T41	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	219987058	219799776	0	0
CsrngAppIfOut_A	219987058	219799776	0	0
FpvSecCmCntAlertCheck_A	219987058	121	0	0
FpvSecCmGenCmdFifoRptrCheck_A	219987058	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	219987058	80	0	0
FpvSecCmMainFsmCheck_A	219987058	80	0	0
FpvSecCmRegWeOnehotCheck_A	219987058	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	219987058	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	219987058	80	0	0
IntrEdnCmdReqDoneKnownO_A	219987058	219799776	0	0
TlAReadyKnownO_A	219987058	219799776	0	0
TlDValidKnownO_A	219987058	219799776	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	219987058	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	219987058	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	219987058	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	219987058	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	219987058	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	219987058	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	219987058	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	219987058	587811	0	314
gen_edn_if_asserts[0].EdnDataStable_A	219987058	22467	0	422
gen_edn_if_asserts[0].EdnEndPointOut_A	219987058	219799776	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	219987058	161383	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	219987058	587811	0	314
gen_edn_if_asserts[1].EdnDataStable_A	219987058	4759	0	132
gen_edn_if_asserts[1].EdnEndPointOut_A	219987058	219799776	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	219987058	161383	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	219987058	587811	0	314
gen_edn_if_asserts[2].EdnDataStable_A	219987058	4529	0	129
gen_edn_if_asserts[2].EdnEndPointOut_A	219987058	219799776	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	219987058	161383	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	219987058	587811	0	314
gen_edn_if_asserts[3].EdnDataStable_A	219987058	4230	0	109
gen_edn_if_asserts[3].EdnEndPointOut_A	219987058	219799776	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	219987058	161383	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	219987058	587811	0	314
gen_edn_if_asserts[4].EdnDataStable_A	219987058	5058	0	95
gen_edn_if_asserts[4].EdnEndPointOut_A	219987058	219799776	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	219987058	161383	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	219987058	587811	0	314
gen_edn_if_asserts[5].EdnDataStable_A	219987058	2845	0	84
gen_edn_if_asserts[5].EdnEndPointOut_A	219987058	219799776	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	219987058	161383	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	219987058	587811	0	314
gen_edn_if_asserts[6].EdnDataStable_A	219987058	5556	0	88
gen_edn_if_asserts[6].EdnEndPointOut_A	219987058	219799776	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	219987058	161383	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	121	0	0
T4	2070	1	0	0
T5	12795	0	0	0
T6	793	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T16	0	1	0	0
T20	9737	0	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	2052	0	0	0
T66	891	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	80	0	0
T17	48871	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T67	0	20	0	0
T68	0	20	0	0
T69	2540	0	0	0
T70	6154	0	0	0
T71	1236	0	0	0
T72	2463	0	0	0
T73	6040	0	0	0
T74	1654	0	0	0
T75	1288	0	0	0
T76	2853	0	0	0
T77	2194	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	80	0	0
T17	48871	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T67	0	20	0	0
T68	0	20	0	0
T69	2540	0	0	0
T70	6154	0	0	0
T71	1236	0	0	0
T72	2463	0	0	0
T73	6040	0	0	0
T74	1654	0	0	0
T75	1288	0	0	0
T76	2853	0	0	0
T77	2194	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	80	0	0
T17	48871	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T67	0	20	0	0
T68	0	20	0	0
T69	2540	0	0	0
T70	6154	0	0	0
T71	1236	0	0	0
T72	2463	0	0	0
T73	6040	0	0	0
T74	1654	0	0	0
T75	1288	0	0	0
T76	2853	0	0	0
T77	2194	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	80	0	0
T17	48871	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T67	0	20	0	0
T68	0	20	0	0
T69	2540	0	0	0
T70	6154	0	0	0
T71	1236	0	0	0
T72	2463	0	0	0
T73	6040	0	0	0
T74	1654	0	0	0
T75	1288	0	0	0
T76	2853	0	0	0
T77	2194	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	80	0	0
T17	48871	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T67	0	20	0	0
T68	0	20	0	0
T69	2540	0	0	0
T70	6154	0	0	0
T71	1236	0	0	0
T72	2463	0	0	0
T73	6040	0	0	0
T74	1654	0	0	0
T75	1288	0	0	0
T76	2853	0	0	0
T77	2194	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	80	0	0
T17	48871	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T67	0	20	0	0
T68	0	20	0	0
T69	2540	0	0	0
T70	6154	0	0	0
T71	1236	0	0	0
T72	2463	0	0	0
T73	6040	0	0	0
T74	1654	0	0	0
T75	1288	0	0	0
T76	2853	0	0	0
T77	2194	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	80	0	0
T17	48871	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T67	0	20	0	0
T68	0	20	0	0
T69	2540	0	0	0
T70	6154	0	0	0
T71	1236	0	0	0
T72	2463	0	0	0
T73	6040	0	0	0
T74	1654	0	0	0
T75	1288	0	0	0
T76	2853	0	0	0
T77	2194	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	80	0	0
T17	48871	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T67	0	20	0	0
T68	0	20	0	0
T69	2540	0	0	0
T70	6154	0	0	0
T71	1236	0	0	0
T72	2463	0	0	0
T73	6040	0	0	0
T74	1654	0	0	0
T75	1288	0	0	0
T76	2853	0	0	0
T77	2194	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	80	0	0
T17	48871	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T67	0	20	0	0
T68	0	20	0	0
T69	2540	0	0	0
T70	6154	0	0	0
T71	1236	0	0	0
T72	2463	0	0	0
T73	6040	0	0	0
T74	1654	0	0	0
T75	1288	0	0	0
T76	2853	0	0	0
T77	2194	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	80	0	0
T17	48871	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T67	0	20	0	0
T68	0	20	0	0
T69	2540	0	0	0
T70	6154	0	0	0
T71	1236	0	0	0
T72	2463	0	0	0
T73	6040	0	0	0
T74	1654	0	0	0
T75	1288	0	0	0
T76	2853	0	0	0
T77	2194	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	80	0	0
T17	48871	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T67	0	20	0	0
T68	0	20	0	0
T69	2540	0	0	0
T70	6154	0	0	0
T71	1236	0	0	0
T72	2463	0	0	0
T73	6040	0	0	0
T74	1654	0	0	0
T75	1288	0	0	0
T76	2853	0	0	0
T77	2194	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	80	0	0
T17	48871	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T67	0	20	0	0
T68	0	20	0	0
T69	2540	0	0	0
T70	6154	0	0	0
T71	1236	0	0	0
T72	2463	0	0	0
T73	6040	0	0	0
T74	1654	0	0	0
T75	1288	0	0	0
T76	2853	0	0	0
T77	2194	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	80	0	0
T17	48871	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T67	0	20	0	0
T68	0	20	0	0
T69	2540	0	0	0
T70	6154	0	0	0
T71	1236	0	0	0
T72	2463	0	0	0
T73	6040	0	0	0
T74	1654	0	0	0
T75	1288	0	0	0
T76	2853	0	0	0
T77	2194	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	587811	0	314
T1	1698	160	0	0
T2	1776	164	0	0
T3	2023	15	0	0
T4	2070	1071	0	0
T10	1982	328	0	0
T21	0	0	0	2
T22	1025	936	0	2
T23	1728	240	0	0
T24	5957	36	0	0
T25	1216	1150	0	2
T26	1537	17	0	0
T40	0	0	0	2
T41	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	22467	0	422
T1	1698	4	0	1
T2	1776	4	0	1
T3	2023	19	0	1
T4	2070	1	0	0
T5	0	0	0	1
T10	1982	0	0	0
T15	0	4	0	0
T20	0	0	0	1
T22	1025	0	0	0
T23	1728	0	0	0
T24	5957	3	0	1
T25	1216	0	0	0
T26	1537	3	0	1
T58	0	4	0	1
T65	0	4	0	1
T66	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	161383	0	0
T4	2070	1110	0	0
T5	12795	0	0	0
T6	793	16	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T20	9737	0	0	0
T30	0	20	0	0
T31	0	30	0	0
T33	0	17	0	0
T34	0	29	0	0
T35	0	1072	0	0
T36	0	468	0	0
T38	0	7	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	192	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	587811	0	314
T1	1698	160	0	0
T2	1776	164	0	0
T3	2023	15	0	0
T4	2070	1071	0	0
T10	1982	328	0	0
T21	0	0	0	2
T22	1025	936	0	2
T23	1728	240	0	0
T24	5957	36	0	0
T25	1216	1150	0	2
T26	1537	17	0	0
T40	0	0	0	2
T41	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	4759	0	132
T4	2070	0	0	0
T10	1982	0	0	0
T11	6312	795	0	1
T12	0	3	0	1
T15	2181	4	0	1
T21	0	1	0	0
T23	1728	4	0	1
T24	5957	56	0	1
T25	1216	0	0	0
T26	1537	0	0	0
T44	0	63	0	1
T47	0	3	0	1
T48	0	3	0	1
T49	0	23	0	1
T58	2796	0	0	0
T65	2052	0	0	0
T84	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	161383	0	0
T4	2070	1110	0	0
T5	12795	0	0	0
T6	793	16	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T20	9737	0	0	0
T30	0	20	0	0
T31	0	30	0	0
T33	0	17	0	0
T34	0	29	0	0
T35	0	1072	0	0
T36	0	468	0	0
T38	0	7	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	192	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	587811	0	314
T1	1698	160	0	0
T2	1776	164	0	0
T3	2023	15	0	0
T4	2070	1071	0	0
T10	1982	328	0	0
T21	0	0	0	2
T22	1025	936	0	2
T23	1728	240	0	0
T24	5957	36	0	0
T25	1216	1150	0	2
T26	1537	17	0	0
T40	0	0	0	2
T41	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	4529	0	129
T4	2070	0	0	0
T10	1982	0	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T24	5957	3	0	1
T25	1216	0	0	0
T26	1537	0	0	0
T34	0	1	0	0
T43	0	8	0	1
T44	0	20	0	1
T50	0	3	0	1
T51	0	99	0	1
T53	0	3	0	1
T56	0	0	0	1
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T85	0	4	0	1
T86	0	4	0	0
T87	0	3	0	1
T88	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	161383	0	0
T4	2070	1110	0	0
T5	12795	0	0	0
T6	793	16	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T20	9737	0	0	0
T30	0	20	0	0
T31	0	30	0	0
T33	0	17	0	0
T34	0	29	0	0
T35	0	1072	0	0
T36	0	468	0	0
T38	0	7	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	192	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	587811	0	314
T1	1698	160	0	0
T2	1776	164	0	0
T3	2023	15	0	0
T4	2070	1071	0	0
T10	1982	328	0	0
T21	0	0	0	2
T22	1025	936	0	2
T23	1728	240	0	0
T24	5957	36	0	0
T25	1216	1150	0	2
T26	1537	17	0	0
T40	0	0	0	2
T41	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	4230	0	109
T4	2070	0	0	0
T5	12795	0	0	0
T6	793	0	0	0
T10	1982	4	0	1
T11	6312	0	0	0
T12	0	25	0	1
T15	2181	0	0	0
T21	0	4	0	0
T26	1537	0	0	0
T44	0	28	0	1
T45	0	11	0	1
T47	0	3	0	1
T51	0	47	0	1
T52	0	16	0	1
T53	0	13	0	1
T55	0	0	0	1
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T84	0	3	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	161383	0	0
T4	2070	1110	0	0
T5	12795	0	0	0
T6	793	16	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T20	9737	0	0	0
T30	0	20	0	0
T31	0	30	0	0
T33	0	17	0	0
T34	0	29	0	0
T35	0	1072	0	0
T36	0	468	0	0
T38	0	7	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	192	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	587811	0	314
T1	1698	160	0	0
T2	1776	164	0	0
T3	2023	15	0	0
T4	2070	1071	0	0
T10	1982	328	0	0
T21	0	0	0	2
T22	1025	936	0	2
T23	1728	240	0	0
T24	5957	36	0	0
T25	1216	1150	0	2
T26	1537	17	0	0
T40	0	0	0	2
T41	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	5058	0	95
T4	2070	0	0	0
T10	1982	0	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T24	5957	21	0	1
T25	1216	0	0	0
T26	1537	0	0	0
T44	0	60	0	1
T45	0	3	0	1
T46	0	4	0	1
T53	0	3	0	1
T54	0	43	0	1
T55	0	15	0	1
T56	0	3	0	1
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T89	0	4	0	1
T90	0	4	0	0
T91	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	161383	0	0
T4	2070	1110	0	0
T5	12795	0	0	0
T6	793	16	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T20	9737	0	0	0
T30	0	20	0	0
T31	0	30	0	0
T33	0	17	0	0
T34	0	29	0	0
T35	0	1072	0	0
T36	0	468	0	0
T38	0	7	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	192	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	587811	0	314
T1	1698	160	0	0
T2	1776	164	0	0
T3	2023	15	0	0
T4	2070	1071	0	0
T10	1982	328	0	0
T21	0	0	0	2
T22	1025	936	0	2
T23	1728	240	0	0
T24	5957	36	0	0
T25	1216	1150	0	2
T26	1537	17	0	0
T40	0	0	0	2
T41	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	2845	0	84
T12	0	3	0	1
T33	455	1	0	0
T35	1761	0	0	0
T43	1891	0	0	0
T44	5428	17	0	1
T47	2536	3	0	1
T48	1802	7	0	1
T49	3187	0	0	0
T52	2940	0	0	0
T54	0	3	0	1
T55	0	42	0	1
T56	0	49	0	1
T80	0	4	0	0
T92	0	3	0	1
T93	3873	0	0	0
T94	1053	0	0	0
T95	0	0	0	1
T96	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	161383	0	0
T4	2070	1110	0	0
T5	12795	0	0	0
T6	793	16	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T20	9737	0	0	0
T30	0	20	0	0
T31	0	30	0	0
T33	0	17	0	0
T34	0	29	0	0
T35	0	1072	0	0
T36	0	468	0	0
T38	0	7	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	192	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	587811	0	314
T1	1698	160	0	0
T2	1776	164	0	0
T3	2023	15	0	0
T4	2070	1071	0	0
T10	1982	328	0	0
T21	0	0	0	2
T22	1025	936	0	2
T23	1728	240	0	0
T24	5957	36	0	0
T25	1216	1150	0	2
T26	1537	17	0	0
T40	0	0	0	2
T41	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2
T80	0	0	0	2
T81	0	0	0	2
T82	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	5556	0	88
T4	2070	0	0	0
T10	1982	0	0	0
T11	6312	0	0	0
T12	0	3	0	1
T15	2181	0	0	0
T24	5957	3	0	1
T25	1216	0	0	0
T26	1537	0	0	0
T44	0	45	0	1
T47	0	3	0	1
T53	0	52	0	1
T54	0	3	0	1
T57	0	34	0	1
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T96	0	19	0	1
T97	0	1112	0	1
T98	0	15	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	219799776	0	0
T1	1698	1603	0	0
T2	1776	1687	0	0
T3	2023	1956	0	0
T4	2070	1960	0	0
T10	1982	1925	0	0
T22	1025	938	0	0
T23	1728	1630	0	0
T24	5957	5902	0	0
T25	1216	1152	0	0
T26	1537	1476	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219987058	161383	0	0
T4	2070	1110	0	0
T5	12795	0	0	0
T6	793	16	0	0
T11	6312	0	0	0
T15	2181	0	0	0
T20	9737	0	0	0
T30	0	20	0	0
T31	0	30	0	0
T33	0	17	0	0
T34	0	29	0	0
T35	0	1072	0	0
T36	0	468	0	0
T38	0	7	0	0
T46	2193	0	0	0
T58	2796	0	0	0
T65	2052	0	0	0
T66	891	0	0	0
T83	0	192	0	0