Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	220428075	9729865	0	0
boot_gen_cmd_rd_A	220428075	78213	0	0
boot_ins_cmd_rd_A	220428075	90436	0	0
ctrl_rd_A	220428075	78093	0	0
err_code_test_rd_A	220428075	88368	0	0
intr_enable_rd_A	220428075	84670	0	0
max_num_reqs_between_reseeds_rd_A	220428075	78034	0	0
regwen_rd_A	220428075	89026	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220428075	9729865	0	0
T30	2282	0	0	0
T34	649	0	0	0
T40	145202	49054	0	0
T41	195214	110536	0	0
T42	0	97624	0	0
T51	2209	0	0	0
T53	2180	0	0	0
T79	0	182499	0	0
T82	0	102097	0	0
T86	2059	0	0	0
T113	0	300178	0	0
T118	3047	0	0	0
T232	0	87077	0	0
T233	0	64781	0	0
T234	0	312816	0	0
T235	0	566332	0	0
T236	1675	0	0	0
T237	2293	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220428075	78213	0	0
T30	2282	0	0	0
T34	649	0	0	0
T40	145202	1509	0	0
T41	195214	0	0	0
T51	2209	0	0	0
T53	2180	0	0	0
T86	2059	0	0	0
T118	3047	0	0	0
T233	0	2012	0	0
T234	0	8846	0	0
T236	1675	0	0	0
T237	2293	0	0	0
T238	0	6721	0	0
T239	0	969	0	0
T240	0	5300	0	0
T241	0	4161	0	0
T242	0	931	0	0
T243	0	1036	0	0
T244	0	2886	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220428075	90436	0	0
T30	2282	0	0	0
T34	649	0	0	0
T40	145202	1675	0	0
T41	195214	0	0	0
T51	2209	0	0	0
T53	2180	0	0	0
T86	2059	0	0	0
T118	3047	0	0	0
T233	0	2273	0	0
T234	0	10359	0	0
T236	1675	0	0	0
T237	2293	0	0	0
T238	0	7921	0	0
T239	0	1302	0	0
T240	0	6290	0	0
T241	0	4774	0	0
T242	0	1043	0	0
T243	0	1145	0	0
T244	0	3347	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220428075	78093	0	0
T30	2282	0	0	0
T34	649	0	0	0
T40	145202	1403	0	0
T41	195214	0	0	0
T51	2209	0	0	0
T53	2180	0	0	0
T86	2059	0	0	0
T118	3047	0	0	0
T134	0	4	0	0
T233	0	2199	0	0
T234	0	8861	0	0
T236	1675	0	0	0
T237	2293	0	0	0
T238	0	6515	0	0
T239	0	1106	0	0
T240	0	5055	0	0
T241	0	4301	0	0
T245	0	4	0	0
T246	0	4	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220428075	88368	0	0
T30	2282	0	0	0
T34	649	0	0	0
T40	145202	1496	0	0
T41	195214	0	0	0
T51	2209	0	0	0
T53	2180	0	0	0
T86	2059	0	0	0
T118	3047	0	0	0
T233	0	2147	0	0
T234	0	9998	0	0
T236	1675	0	0	0
T237	2293	0	0	0
T238	0	7598	0	0
T239	0	1150	0	0
T240	0	5952	0	0
T241	0	5449	0	0
T242	0	1189	0	0
T243	0	1119	0	0
T244	0	3325	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220428075	84670	0	0
T5	12795	125	0	0
T6	793	0	0	0
T20	9737	0	0	0
T21	4597	0	0	0
T40	0	1736	0	0
T45	5401	0	0	0
T46	2193	0	0	0
T47	2536	0	0	0
T93	3873	0	0	0
T117	2082	0	0	0
T233	0	2111	0	0
T234	0	9631	0	0
T238	0	6700	0	0
T239	0	1287	0	0
T247	0	13	0	0
T248	0	61	0	0
T249	0	53	0	0
T250	0	7	0	0
T251	2130	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220428075	78034	0	0
T30	2282	0	0	0
T34	649	0	0	0
T40	145202	1348	0	0
T41	195214	0	0	0
T51	2209	0	0	0
T53	2180	0	0	0
T86	2059	0	0	0
T118	3047	0	0	0
T233	0	1639	0	0
T234	0	9398	0	0
T236	1675	0	0	0
T237	2293	0	0	0
T238	0	6819	0	0
T239	0	915	0	0
T240	0	5262	0	0
T241	0	4481	0	0
T242	0	1047	0	0
T243	0	1109	0	0
T244	0	2968	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220428075	89026	0	0
T30	2282	0	0	0
T34	649	0	0	0
T40	145202	1554	0	0
T41	195214	0	0	0
T51	2209	0	0	0
T53	2180	0	0	0
T86	2059	0	0	0
T118	3047	0	0	0
T233	0	2205	0	0
T234	0	10042	0	0
T236	1675	0	0	0
T237	2293	0	0	0
T238	0	7762	0	0
T239	0	1320	0	0
T240	0	6118	0	0
T241	0	5043	0	0
T242	0	1307	0	0
T243	0	1088	0	0
T244	0	3150	0	0