Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	98.25	93.97	97.02	92.44	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.23	99.92	92.75	82.54	92.44	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T21,T15

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T17,T18
1	0	Covered	T4,T30,T6

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T20	Yes	T1,T3,T20	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T20	Yes	T1,T3,T20	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T20	Yes	T1,T3,T20	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T20	Yes	T1,T3,T20	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T3,T34,T35	Yes	T3,T34,T35	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T20	Yes	T1,T3,T20	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T20	Yes	T1,T3,T20	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T20	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T2,T3,T20	Yes	T2,T3,T20	INPUT
edn_i[1].edn_req	Yes	Yes	T4,T10,T12	Yes	T4,T10,T12	INPUT
edn_i[2].edn_req	Yes	Yes	T21,T9,T10	Yes	T21,T9,T10	INPUT
edn_i[3].edn_req	Yes	Yes	T22,T10,T11	Yes	T22,T10,T11	INPUT
edn_i[4].edn_req	Yes	Yes	T1,T21,T9	Yes	T1,T21,T9	INPUT
edn_i[5].edn_req	Yes	Yes	T9,T36,T37	Yes	T9,T36,T37	INPUT
edn_i[6].edn_req	Yes	Yes	T9,T10,T38	Yes	T9,T10,T38	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T3,T20	Yes	T2,T3,T20	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T2,T3,T20	Yes	T2,T3,T20	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T2,T3,T20	Yes	T2,T3,T20	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T10,T12,T39	Yes	T10,T12,T39	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T10,T19,T40	Yes	T10,T12,T39	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T10,T12,T39	Yes	T10,T12,T39	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T21,T9,T10	Yes	T21,T9,T10	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T9,T12,T41	Yes	T21,T9,T15	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T21,T9,T10	Yes	T21,T9,T10	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T10,T11,T38	Yes	T22,T10,T11	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T10,T42,T43	Yes	T10,T42,T44	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T22,T10,T11	Yes	T22,T10,T11	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T1,T9,T45	Yes	T1,T9,T45	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T9,T42,T19	Yes	T9,T45,T42	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T1,T21,T9	Yes	T1,T21,T9	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T9,T36,T37	Yes	T9,T36,T37	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T9,T19,T46	Yes	T9,T42,T19	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T9,T36,T37	Yes	T9,T36,T37	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T9,T10,T38	Yes	T9,T10,T38	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T9,T10,T42	Yes	T9,T10,T42	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T9,T10,T38	Yes	T9,T10,T38	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T20,T9	Yes	T3,T9,T10	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T2,T3,T20	Yes	T3,T20,T21	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T1,T15,T30	Yes	T1,T15,T30	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T21,T15	Yes	T1,T21,T15	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T47,T30	Yes	T4,T47,T30	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T21,T15	Yes	T1,T21,T15	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T47,T30	Yes	T4,T47,T30	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T3,T5,T48	Yes	T3,T5,T48	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T3,T5,T48	Yes	T3,T5,T48	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	217899114	217711050	0	0
CsrngAppIfOut_A	217899114	217711050	0	0
FpvSecCmCntAlertCheck_A	217899114	122	0	0
FpvSecCmGenCmdFifoRptrCheck_A	217899114	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	217899114	80	0	0
FpvSecCmMainFsmCheck_A	217899114	80	0	0
FpvSecCmRegWeOnehotCheck_A	217899114	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	217899114	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	217899114	80	0	0
IntrEdnCmdReqDoneKnownO_A	217899114	217711050	0	0
TlAReadyKnownO_A	217899114	217711050	0	0
TlDValidKnownO_A	217899114	217711050	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	217899114	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	217899114	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	217899114	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	217899114	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	217899114	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	217899114	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	217899114	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	217899114	561815	0	324
gen_edn_if_asserts[0].EdnDataStable_A	217899114	20644	0	421
gen_edn_if_asserts[0].EdnEndPointOut_A	217899114	217711050	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	217899114	153496	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	217899114	561815	0	324
gen_edn_if_asserts[1].EdnDataStable_A	217899114	4694	0	137
gen_edn_if_asserts[1].EdnEndPointOut_A	217899114	217711050	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	217899114	153496	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	217899114	561815	0	324
gen_edn_if_asserts[2].EdnDataStable_A	217899114	6354	0	135
gen_edn_if_asserts[2].EdnEndPointOut_A	217899114	217711050	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	217899114	153496	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	217899114	561815	0	324
gen_edn_if_asserts[3].EdnDataStable_A	217899114	4699	0	122
gen_edn_if_asserts[3].EdnEndPointOut_A	217899114	217711050	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	217899114	153496	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	217899114	561815	0	324
gen_edn_if_asserts[4].EdnDataStable_A	217899114	3508	0	104
gen_edn_if_asserts[4].EdnEndPointOut_A	217899114	217711050	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	217899114	153496	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	217899114	561815	0	324
gen_edn_if_asserts[5].EdnDataStable_A	217899114	4219	0	89
gen_edn_if_asserts[5].EdnEndPointOut_A	217899114	217711050	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	217899114	153496	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	217899114	561815	0	324
gen_edn_if_asserts[6].EdnDataStable_A	217899114	2956	0	85
gen_edn_if_asserts[6].EdnEndPointOut_A	217899114	217711050	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	217899114	153496	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	217711050	0	0
T1	2073	1995	0	0
T2	1200	1145	0	0
T3	312798	312790	0	0
T4	3042	2891	0	0
T9	6192	6140	0	0
T10	6242	6174	0	0
T15	2005	1922	0	0
T20	3740	3680	0	0
T21	2491	2391	0	0
T22	1007	930	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	217711050	0	0
T1	2073	1995	0	0
T2	1200	1145	0	0
T3	312798	312790	0	0
T4	3042	2891	0	0
T9	6192	6140	0	0
T10	6242	6174	0	0
T15	2005	1922	0	0
T20	3740	3680	0	0
T21	2491	2391	0	0
T22	1007	930	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	122	0	0
T4	3042	1	0	0
T5	4912	0	0	0
T6	0	1	0	0
T7	0	1	0	0
T9	6192	0	0	0
T10	6242	0	0	0
T11	2024	0	0	0
T15	2005	0	0	0
T16	0	10	0	0
T22	1007	0	0	0
T30	616	0	0	0
T47	1236	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	1508	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	80	0	0
T16	28802	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T56	0	20	0	0
T57	0	10	0	0
T58	2615	0	0	0
T59	1984	0	0	0
T60	2589	0	0	0
T61	2710	0	0	0
T62	622381	0	0	0
T63	387	0	0	0
T64	4555	0	0	0
T65	4174	0	0	0
T66	2291	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	80	0	0
T16	28802	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T56	0	20	0	0
T57	0	10	0	0
T58	2615	0	0	0
T59	1984	0	0	0
T60	2589	0	0	0
T61	2710	0	0	0
T62	622381	0	0	0
T63	387	0	0	0
T64	4555	0	0	0
T65	4174	0	0	0
T66	2291	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	80	0	0
T16	28802	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T56	0	20	0	0
T57	0	10	0	0
T58	2615	0	0	0
T59	1984	0	0	0
T60	2589	0	0	0
T61	2710	0	0	0
T62	622381	0	0	0
T63	387	0	0	0
T64	4555	0	0	0
T65	4174	0	0	0
T66	2291	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	80	0	0
T16	28802	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T56	0	20	0	0
T57	0	10	0	0
T58	2615	0	0	0
T59	1984	0	0	0
T60	2589	0	0	0
T61	2710	0	0	0
T62	622381	0	0	0
T63	387	0	0	0
T64	4555	0	0	0
T65	4174	0	0	0
T66	2291	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	80	0	0
T16	28802	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T56	0	20	0	0
T57	0	10	0	0
T58	2615	0	0	0
T59	1984	0	0	0
T60	2589	0	0	0
T61	2710	0	0	0
T62	622381	0	0	0
T63	387	0	0	0
T64	4555	0	0	0
T65	4174	0	0	0
T66	2291	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	80	0	0
T16	28802	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T56	0	20	0	0
T57	0	10	0	0
T58	2615	0	0	0
T59	1984	0	0	0
T60	2589	0	0	0
T61	2710	0	0	0
T62	622381	0	0	0
T63	387	0	0	0
T64	4555	0	0	0
T65	4174	0	0	0
T66	2291	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	217711050	0	0
T1	2073	1995	0	0
T2	1200	1145	0	0
T3	312798	312790	0	0
T4	3042	2891	0	0
T9	6192	6140	0	0
T10	6242	6174	0	0
T15	2005	1922	0	0
T20	3740	3680	0	0
T21	2491	2391	0	0
T22	1007	930	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	217711050	0	0
T1	2073	1995	0	0
T2	1200	1145	0	0
T3	312798	312790	0	0
T4	3042	2891	0	0
T9	6192	6140	0	0
T10	6242	6174	0	0
T15	2005	1922	0	0
T20	3740	3680	0	0
T21	2491	2391	0	0
T22	1007	930	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	217711050	0	0
T1	2073	1995	0	0
T2	1200	1145	0	0
T3	312798	312790	0	0
T4	3042	2891	0	0
T9	6192	6140	0	0
T10	6242	6174	0	0
T15	2005	1922	0	0
T20	3740	3680	0	0
T21	2491	2391	0	0
T22	1007	930	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	80	0	0
T16	28802	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T56	0	20	0	0
T57	0	10	0	0
T58	2615	0	0	0
T59	1984	0	0	0
T60	2589	0	0	0
T61	2710	0	0	0
T62	622381	0	0	0
T63	387	0	0	0
T64	4555	0	0	0
T65	4174	0	0	0
T66	2291	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	80	0	0
T16	28802	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T56	0	20	0	0
T57	0	10	0	0
T58	2615	0	0	0
T59	1984	0	0	0
T60	2589	0	0	0
T61	2710	0	0	0
T62	622381	0	0	0
T63	387	0	0	0
T64	4555	0	0	0
T65	4174	0	0	0
T66	2291	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	80	0	0
T16	28802	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T56	0	20	0	0
T57	0	10	0	0
T58	2615	0	0	0
T59	1984	0	0	0
T60	2589	0	0	0
T61	2710	0	0	0
T62	622381	0	0	0
T63	387	0	0	0
T64	4555	0	0	0
T65	4174	0	0	0
T66	2291	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	80	0	0
T16	28802	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T56	0	20	0	0
T57	0	10	0	0
T58	2615	0	0	0
T59	1984	0	0	0
T60	2589	0	0	0
T61	2710	0	0	0
T62	622381	0	0	0
T63	387	0	0	0
T64	4555	0	0	0
T65	4174	0	0	0
T66	2291	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	80	0	0
T16	28802	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T56	0	20	0	0
T57	0	10	0	0
T58	2615	0	0	0
T59	1984	0	0	0
T60	2589	0	0	0
T61	2710	0	0	0
T62	622381	0	0	0
T63	387	0	0	0
T64	4555	0	0	0
T65	4174	0	0	0
T66	2291	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	80	0	0
T16	28802	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T56	0	20	0	0
T57	0	10	0	0
T58	2615	0	0	0
T59	1984	0	0	0
T60	2589	0	0	0
T61	2710	0	0	0
T62	622381	0	0	0
T63	387	0	0	0
T64	4555	0	0	0
T65	4174	0	0	0
T66	2291	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	80	0	0
T16	28802	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T56	0	20	0	0
T57	0	10	0	0
T58	2615	0	0	0
T59	1984	0	0	0
T60	2589	0	0	0
T61	2710	0	0	0
T62	622381	0	0	0
T63	387	0	0	0
T64	4555	0	0	0
T65	4174	0	0	0
T66	2291	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	561815	0	324
T1	2073	204	0	0
T2	1200	67	0	0
T3	312798	1041	0	2
T4	3042	1208	0	0
T9	6192	83	0	0
T10	6242	85	0	0
T11	0	0	0	2
T15	2005	538	0	0
T20	3740	41	0	0
T21	2491	135	0	0
T22	1007	78	0	0
T35	0	0	0	2
T47	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	20644	0	421
T2	1200	3	0	1
T3	312798	71	0	0
T4	3042	0	0	0
T5	0	6	0	1
T9	6192	3	0	1
T10	6242	0	0	0
T15	2005	0	0	0
T20	3740	20	0	1
T21	2491	0	0	0
T22	1007	0	0	0
T34	0	0	0	1
T48	0	3	0	1
T55	1508	22	0	1
T73	0	28	0	1
T74	0	8	0	1
T75	0	4	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	217711050	0	0
T1	2073	1995	0	0
T2	1200	1145	0	0
T3	312798	312790	0	0
T4	3042	2891	0	0
T9	6192	6140	0	0
T10	6242	6174	0	0
T15	2005	1922	0	0
T20	3740	3680	0	0
T21	2491	2391	0	0
T22	1007	930	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	153496	0	0
T4	3042	1159	0	0
T5	4912	0	0	0
T6	0	334	0	0
T7	0	387	0	0
T8	0	256	0	0
T9	6192	0	0	0
T10	6242	0	0	0
T11	2024	0	0	0
T15	2005	0	0	0
T22	1007	0	0	0
T30	616	302	0	0
T47	1236	0	0	0
T55	1508	0	0	0
T76	0	1110	0	0
T77	0	615	0	0
T78	0	402	0	0
T79	0	398	0	0
T80	0	399	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	561815	0	324
T1	2073	204	0	0
T2	1200	67	0	0
T3	312798	1041	0	2
T4	3042	1208	0	0
T9	6192	83	0	0
T10	6242	85	0	0
T11	0	0	0	2
T15	2005	538	0	0
T20	3740	41	0	0
T21	2491	135	0	0
T22	1007	78	0	0
T35	0	0	0	2
T47	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	4694	0	137
T5	4912	0	0	0
T10	6242	53	0	1
T11	2024	0	0	0
T12	0	3	0	1
T13	0	65	0	1
T15	2005	0	0	0
T19	0	47	0	1
T30	616	0	0	0
T37	0	3	0	1
T39	0	4	0	1
T40	0	51	0	1
T47	1236	0	0	0
T48	4910	0	0	0
T55	1508	0	0	0
T71	0	1	0	0
T73	24277	0	0	0
T74	2305	0	0	0
T81	0	3	0	1
T82	0	4	0	0
T83	0	0	0	1
T84	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	217711050	0	0
T1	2073	1995	0	0
T2	1200	1145	0	0
T3	312798	312790	0	0
T4	3042	2891	0	0
T9	6192	6140	0	0
T10	6242	6174	0	0
T15	2005	1922	0	0
T20	3740	3680	0	0
T21	2491	2391	0	0
T22	1007	930	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	153496	0	0
T4	3042	1159	0	0
T5	4912	0	0	0
T6	0	334	0	0
T7	0	387	0	0
T8	0	256	0	0
T9	6192	0	0	0
T10	6242	0	0	0
T11	2024	0	0	0
T15	2005	0	0	0
T22	1007	0	0	0
T30	616	302	0	0
T47	1236	0	0	0
T55	1508	0	0	0
T76	0	1110	0	0
T77	0	615	0	0
T78	0	402	0	0
T79	0	398	0	0
T80	0	399	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	561815	0	324
T1	2073	204	0	0
T2	1200	67	0	0
T3	312798	1041	0	2
T4	3042	1208	0	0
T9	6192	83	0	0
T10	6242	85	0	0
T11	0	0	0	2
T15	2005	538	0	0
T20	3740	41	0	0
T21	2491	135	0	0
T22	1007	78	0	0
T35	0	0	0	2
T47	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	6354	0	135
T4	3042	0	0	0
T5	4912	0	0	0
T9	6192	592	0	1
T10	6242	3	0	1
T11	2024	0	0	0
T12	0	70	0	1
T15	2005	4	0	1
T19	0	3	0	1
T21	2491	4	0	1
T22	1007	0	0	0
T40	0	3	0	1
T42	0	3	0	1
T47	1236	0	0	0
T55	1508	0	0	0
T67	0	4	0	0
T81	0	3	0	1
T83	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	217711050	0	0
T1	2073	1995	0	0
T2	1200	1145	0	0
T3	312798	312790	0	0
T4	3042	2891	0	0
T9	6192	6140	0	0
T10	6242	6174	0	0
T15	2005	1922	0	0
T20	3740	3680	0	0
T21	2491	2391	0	0
T22	1007	930	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	153496	0	0
T4	3042	1159	0	0
T5	4912	0	0	0
T6	0	334	0	0
T7	0	387	0	0
T8	0	256	0	0
T9	6192	0	0	0
T10	6242	0	0	0
T11	2024	0	0	0
T15	2005	0	0	0
T22	1007	0	0	0
T30	616	302	0	0
T47	1236	0	0	0
T55	1508	0	0	0
T76	0	1110	0	0
T77	0	615	0	0
T78	0	402	0	0
T79	0	398	0	0
T80	0	399	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	561815	0	324
T1	2073	204	0	0
T2	1200	67	0	0
T3	312798	1041	0	2
T4	3042	1208	0	0
T9	6192	83	0	0
T10	6242	85	0	0
T11	0	0	0	2
T15	2005	538	0	0
T20	3740	41	0	0
T21	2491	135	0	0
T22	1007	78	0	0
T35	0	0	0	2
T47	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	4699	0	122
T5	4912	0	0	0
T10	6242	32	0	1
T11	2024	4	0	0
T15	2005	0	0	0
T22	1007	3	0	1
T30	616	0	0	0
T38	0	4	0	0
T41	0	0	0	1
T42	0	53	0	1
T43	0	23	0	1
T44	0	4	0	1
T46	0	0	0	1
T47	1236	0	0	0
T48	4910	0	0	0
T55	1508	0	0	0
T73	24277	0	0	0
T81	0	21	0	1
T84	0	3	0	1
T85	0	4	0	0
T86	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	217711050	0	0
T1	2073	1995	0	0
T2	1200	1145	0	0
T3	312798	312790	0	0
T4	3042	2891	0	0
T9	6192	6140	0	0
T10	6242	6174	0	0
T15	2005	1922	0	0
T20	3740	3680	0	0
T21	2491	2391	0	0
T22	1007	930	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	153496	0	0
T4	3042	1159	0	0
T5	4912	0	0	0
T6	0	334	0	0
T7	0	387	0	0
T8	0	256	0	0
T9	6192	0	0	0
T10	6242	0	0	0
T11	2024	0	0	0
T15	2005	0	0	0
T22	1007	0	0	0
T30	616	302	0	0
T47	1236	0	0	0
T55	1508	0	0	0
T76	0	1110	0	0
T77	0	615	0	0
T78	0	402	0	0
T79	0	398	0	0
T80	0	399	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	561815	0	324
T1	2073	204	0	0
T2	1200	67	0	0
T3	312798	1041	0	2
T4	3042	1208	0	0
T9	6192	83	0	0
T10	6242	85	0	0
T11	0	0	0	2
T15	2005	538	0	0
T20	3740	41	0	0
T21	2491	135	0	0
T22	1007	78	0	0
T35	0	0	0	2
T47	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	3508	0	104
T1	2073	8	0	1
T2	1200	0	0	0
T3	312798	0	0	0
T4	3042	0	0	0
T9	6192	19	0	1
T10	6242	0	0	0
T15	2005	0	0	0
T19	0	38	0	1
T20	3740	0	0	0
T21	2491	4	0	0
T22	1007	0	0	0
T41	0	0	0	1
T42	0	34	0	1
T45	0	4	0	1
T81	0	3	0	1
T83	0	15	0	1
T84	0	15	0	1
T86	0	5	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	217711050	0	0
T1	2073	1995	0	0
T2	1200	1145	0	0
T3	312798	312790	0	0
T4	3042	2891	0	0
T9	6192	6140	0	0
T10	6242	6174	0	0
T15	2005	1922	0	0
T20	3740	3680	0	0
T21	2491	2391	0	0
T22	1007	930	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	153496	0	0
T4	3042	1159	0	0
T5	4912	0	0	0
T6	0	334	0	0
T7	0	387	0	0
T8	0	256	0	0
T9	6192	0	0	0
T10	6242	0	0	0
T11	2024	0	0	0
T15	2005	0	0	0
T22	1007	0	0	0
T30	616	302	0	0
T47	1236	0	0	0
T55	1508	0	0	0
T76	0	1110	0	0
T77	0	615	0	0
T78	0	402	0	0
T79	0	398	0	0
T80	0	399	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	561815	0	324
T1	2073	204	0	0
T2	1200	67	0	0
T3	312798	1041	0	2
T4	3042	1208	0	0
T9	6192	83	0	0
T10	6242	85	0	0
T11	0	0	0	2
T15	2005	538	0	0
T20	3740	41	0	0
T21	2491	135	0	0
T22	1007	78	0	0
T35	0	0	0	2
T47	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	4219	0	89
T5	4912	0	0	0
T9	6192	45	0	1
T10	6242	0	0	0
T11	2024	0	0	0
T15	2005	0	0	0
T19	0	56	0	1
T22	1007	0	0	0
T30	616	0	0	0
T36	0	4	0	0
T37	0	3	0	1
T41	0	0	0	1
T42	0	3	0	1
T46	0	0	0	1
T47	1236	0	0	0
T48	4910	0	0	0
T55	1508	0	0	0
T82	0	4	0	1
T84	0	4	0	1
T86	0	3	0	1
T87	0	3	0	1
T88	0	4	0	0

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	217711050	0	0
T1	2073	1995	0	0
T2	1200	1145	0	0
T3	312798	312790	0	0
T4	3042	2891	0	0
T9	6192	6140	0	0
T10	6242	6174	0	0
T15	2005	1922	0	0
T20	3740	3680	0	0
T21	2491	2391	0	0
T22	1007	930	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	153496	0	0
T4	3042	1159	0	0
T5	4912	0	0	0
T6	0	334	0	0
T7	0	387	0	0
T8	0	256	0	0
T9	6192	0	0	0
T10	6242	0	0	0
T11	2024	0	0	0
T15	2005	0	0	0
T22	1007	0	0	0
T30	616	302	0	0
T47	1236	0	0	0
T55	1508	0	0	0
T76	0	1110	0	0
T77	0	615	0	0
T78	0	402	0	0
T79	0	398	0	0
T80	0	399	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	561815	0	324
T1	2073	204	0	0
T2	1200	67	0	0
T3	312798	1041	0	2
T4	3042	1208	0	0
T9	6192	83	0	0
T10	6242	85	0	0
T11	0	0	0	2
T15	2005	538	0	0
T20	3740	41	0	0
T21	2491	135	0	0
T22	1007	78	0	0
T35	0	0	0	2
T47	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	2956	0	85
T5	4912	0	0	0
T9	6192	26	0	1
T10	6242	651	0	1
T11	2024	0	0	0
T15	2005	0	0	0
T22	1007	0	0	0
T30	616	0	0	0
T38	0	4	0	1
T41	0	3	0	1
T42	0	11	0	1
T43	0	22	0	1
T46	0	12	0	1
T47	1236	0	0	0
T48	4910	0	0	0
T55	1508	0	0	0
T64	0	0	0	1
T86	0	24	0	1
T89	0	53	0	1
T90	0	1	0	0

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	217711050	0	0
T1	2073	1995	0	0
T2	1200	1145	0	0
T3	312798	312790	0	0
T4	3042	2891	0	0
T9	6192	6140	0	0
T10	6242	6174	0	0
T15	2005	1922	0	0
T20	3740	3680	0	0
T21	2491	2391	0	0
T22	1007	930	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217899114	153496	0	0
T4	3042	1159	0	0
T5	4912	0	0	0
T6	0	334	0	0
T7	0	387	0	0
T8	0	256	0	0
T9	6192	0	0	0
T10	6242	0	0	0
T11	2024	0	0	0
T15	2005	0	0	0
T22	1007	0	0	0
T30	616	302	0	0
T47	1236	0	0	0
T55	1508	0	0	0
T76	0	1110	0	0
T77	0	615	0	0
T78	0	402	0	0
T79	0	398	0	0
T80	0	399	0	0