Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	218409546	9891870	0	0
boot_gen_cmd_rd_A	218409546	56638	0	0
boot_ins_cmd_rd_A	218409546	64701	0	0
ctrl_rd_A	218409546	58007	0	0
err_code_test_rd_A	218409546	65824	0	0
intr_enable_rd_A	218409546	63171	0	0
max_num_reqs_between_reseeds_rd_A	218409546	58060	0	0
regwen_rd_A	218409546	66183	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218409546	9891870	0	0
T3	312798	178018	0	0
T4	3042	0	0	0
T9	6192	0	0	0
T10	6242	0	0	0
T11	2024	0	0	0
T15	2005	0	0	0
T20	3740	0	0	0
T21	2491	0	0	0
T22	1007	0	0	0
T34	0	88653	0	0
T35	0	228183	0	0
T55	1508	0	0	0
T62	0	347960	0	0
T70	0	121668	0	0
T96	0	165836	0	0
T221	0	73879	0	0
T222	0	259979	0	0
T223	0	162265	0	0
T224	0	587117	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218409546	56638	0	0
T50	1296	0	0	0
T95	1388	0	0	0
T222	707923	3946	0	0
T225	0	2641	0	0
T226	0	6463	0	0
T227	0	1285	0	0
T228	0	4141	0	0
T229	0	2645	0	0
T230	0	8965	0	0
T231	0	9413	0	0
T232	0	3435	0	0
T233	0	1138	0	0
T234	2237	0	0	0
T235	1581	0	0	0
T236	2077	0	0	0
T237	11458	0	0	0
T238	1359	0	0	0
T239	1614	0	0	0
T240	1154	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218409546	64701	0	0
T50	1296	0	0	0
T95	1388	0	0	0
T222	707923	4663	0	0
T225	0	2943	0	0
T226	0	7689	0	0
T227	0	1473	0	0
T228	0	4751	0	0
T229	0	2877	0	0
T230	0	10271	0	0
T231	0	10581	0	0
T232	0	4172	0	0
T233	0	1128	0	0
T234	2237	0	0	0
T235	1581	0	0	0
T236	2077	0	0	0
T237	11458	0	0	0
T238	1359	0	0	0
T239	1614	0	0	0
T240	1154	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218409546	58007	0	0
T41	2742	0	0	0
T84	3161	0	0	0
T86	4087	0	0	0
T96	406497	0	0	0
T100	24885	6	0	0
T101	6808	0	0	0
T103	0	3	0	0
T105	2205	0	0	0
T106	2842	0	0	0
T107	2260	0	0	0
T175	2376	0	0	0
T222	0	4486	0	0
T225	0	2739	0	0
T226	0	7262	0	0
T227	0	1176	0	0
T228	0	4334	0	0
T229	0	2346	0	0
T241	0	1	0	0
T242	0	1	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218409546	65824	0	0
T50	1296	0	0	0
T95	1388	0	0	0
T222	707923	4791	0	0
T225	0	3082	0	0
T226	0	7330	0	0
T227	0	1241	0	0
T228	0	5138	0	0
T229	0	2832	0	0
T230	0	10321	0	0
T231	0	11376	0	0
T232	0	4103	0	0
T233	0	1146	0	0
T234	2237	0	0	0
T235	1581	0	0	0
T236	2077	0	0	0
T237	11458	0	0	0
T238	1359	0	0	0
T239	1614	0	0	0
T240	1154	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218409546	63171	0	0
T6	762	0	0	0
T12	1308	0	0	0
T36	731	0	0	0
T39	1940	0	0	0
T48	4910	22	0	0
T67	1633	0	0	0
T68	1458	0	0	0
T73	24277	0	0	0
T74	2305	0	0	0
T75	2227	0	0	0
T100	0	58	0	0
T222	0	4278	0	0
T225	0	2702	0	0
T226	0	7344	0	0
T227	0	1392	0	0
T228	0	4777	0	0
T229	0	3035	0	0
T243	0	31	0	0
T244	0	8	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218409546	58060	0	0
T50	1296	0	0	0
T95	1388	0	0	0
T222	707923	3985	0	0
T225	0	2613	0	0
T226	0	7042	0	0
T227	0	1270	0	0
T228	0	4322	0	0
T229	0	2455	0	0
T230	0	9002	0	0
T231	0	9368	0	0
T232	0	3632	0	0
T233	0	1013	0	0
T234	2237	0	0	0
T235	1581	0	0	0
T236	2077	0	0	0
T237	11458	0	0	0
T238	1359	0	0	0
T239	1614	0	0	0
T240	1154	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218409546	66183	0	0
T50	1296	0	0	0
T95	1388	0	0	0
T222	707923	5007	0	0
T225	0	2988	0	0
T226	0	7776	0	0
T227	0	1191	0	0
T228	0	4737	0	0
T229	0	2686	0	0
T230	0	10173	0	0
T231	0	11029	0	0
T232	0	4145	0	0
T233	0	1219	0	0
T234	2237	0	0	0
T235	1581	0	0	0
T236	2077	0	0	0
T237	11458	0	0	0
T238	1359	0	0	0
T239	1614	0	0	0
T240	1154	0	0	0