Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.39	98.25	93.91	97.02	93.02	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.31	99.92	92.66	82.54	93.02	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T7,T8,T15

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T20
1	0	Covered	T4,T5,T34

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T7	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T3,T7,T8	Yes	T1,T3,T7	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T7,*T8	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	INPUT
edn_i[1].edn_req	Yes	Yes	T24,T43,T44	Yes	T24,T43,T44	INPUT
edn_i[2].edn_req	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	INPUT
edn_i[3].edn_req	Yes	Yes	T3,T11,T45	Yes	T3,T11,T45	INPUT
edn_i[4].edn_req	Yes	Yes	T3,T4,T43	Yes	T3,T4,T43	INPUT
edn_i[5].edn_req	Yes	Yes	T43,T45,T46	Yes	T43,T45,T46	INPUT
edn_i[6].edn_req	Yes	Yes	T3,T47,T43	Yes	T3,T47,T43	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T24,T26,T48	Yes	T24,T26,T49	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T24,T43,T44	Yes	T24,T43,T44	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T24,T43,T44	Yes	T24,T43,T44	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T24,T43,T44	Yes	T24,T43,T44	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T3,T44,T46	Yes	T3,T7,T8	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T3,T45,T46	Yes	T3,T11,T45	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T3,T46,T50	Yes	T3,T11,T45	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T3,T11,T45	Yes	T3,T11,T45	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T4,T43,T51	Yes	T4,T43,T51	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T4,T43,T45	Yes	T4,T43,T51	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T3,T4,T43	Yes	T3,T4,T43	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T43,T45,T46	Yes	T43,T45,T46	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T45,T13,T52	Yes	T45,T13,T52	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T43,T45,T46	Yes	T43,T45,T46	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T47,T43,T12	Yes	T3,T47,T43	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T43,T53,T14	Yes	T43,T12,T53	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T3,T47,T43	Yes	T3,T47,T43	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T24,T26	Yes	T3,T11,T24	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T24,T26	Yes	T3,T24,T26	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T7,T8,T48	Yes	T7,T8,T48	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T3,T7,T8	Yes	T3,T7,T8	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T6,T54,T40	Yes	T6,T54,T40	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T6,T54	Yes	T4,T6,T54	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	196914512	196735478	0	0
CsrngAppIfOut_A	196914512	196735478	0	0
FpvSecCmCntAlertCheck_A	196914512	110	0	0
FpvSecCmGenCmdFifoRptrCheck_A	196914512	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	196914512	70	0	0
FpvSecCmMainFsmCheck_A	196914512	70	0	0
FpvSecCmRegWeOnehotCheck_A	196914512	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	196914512	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	196914512	70	0	0
IntrEdnCmdReqDoneKnownO_A	196914512	196735478	0	0
TlAReadyKnownO_A	196914512	196735478	0	0
TlDValidKnownO_A	196914512	196735478	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	196914512	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	196914512	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	196914512	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	196914512	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	196914512	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	196914512	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	196914512	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	196914512	564150	0	312
gen_edn_if_asserts[0].EdnDataStable_A	196914512	72667	0	411
gen_edn_if_asserts[0].EdnEndPointOut_A	196914512	196735478	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	196914512	147493	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	196914512	564150	0	312
gen_edn_if_asserts[1].EdnDataStable_A	196914512	4798	0	141
gen_edn_if_asserts[1].EdnEndPointOut_A	196914512	196735478	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	196914512	147493	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	196914512	564150	0	312
gen_edn_if_asserts[2].EdnDataStable_A	196914512	6052	0	127
gen_edn_if_asserts[2].EdnEndPointOut_A	196914512	196735478	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	196914512	147493	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	196914512	564150	0	312
gen_edn_if_asserts[3].EdnDataStable_A	196914512	5737	0	117
gen_edn_if_asserts[3].EdnEndPointOut_A	196914512	196735478	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	196914512	147493	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	196914512	564150	0	312
gen_edn_if_asserts[4].EdnDataStable_A	196914512	3632	0	110
gen_edn_if_asserts[4].EdnEndPointOut_A	196914512	196735478	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	196914512	147493	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	196914512	564150	0	312
gen_edn_if_asserts[5].EdnDataStable_A	196914512	2609	0	108
gen_edn_if_asserts[5].EdnEndPointOut_A	196914512	196735478	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	196914512	147493	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	196914512	564150	0	312
gen_edn_if_asserts[6].EdnDataStable_A	196914512	3754	0	87
gen_edn_if_asserts[6].EdnEndPointOut_A	196914512	196735478	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	196914512	147493	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	110	0	0
T5	2223	1	0	0
T6	31003	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T23	7450	0	0	0
T27	1127	0	0	0
T43	3261	0	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T51	2454	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	1245	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	70	0	0
T18	43973	20	0	0
T19	0	10	0	0
T20	0	10	0	0
T63	0	10	0	0
T64	0	20	0	0
T65	1900	0	0	0
T66	2622	0	0	0
T67	286235	0	0	0
T68	4251	0	0	0
T69	2690	0	0	0
T70	10811	0	0	0
T71	811	0	0	0
T72	3579	0	0	0
T73	6498	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	70	0	0
T18	43973	20	0	0
T19	0	10	0	0
T20	0	10	0	0
T63	0	10	0	0
T64	0	20	0	0
T65	1900	0	0	0
T66	2622	0	0	0
T67	286235	0	0	0
T68	4251	0	0	0
T69	2690	0	0	0
T70	10811	0	0	0
T71	811	0	0	0
T72	3579	0	0	0
T73	6498	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	70	0	0
T18	43973	20	0	0
T19	0	10	0	0
T20	0	10	0	0
T63	0	10	0	0
T64	0	20	0	0
T65	1900	0	0	0
T66	2622	0	0	0
T67	286235	0	0	0
T68	4251	0	0	0
T69	2690	0	0	0
T70	10811	0	0	0
T71	811	0	0	0
T72	3579	0	0	0
T73	6498	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	70	0	0
T18	43973	20	0	0
T19	0	10	0	0
T20	0	10	0	0
T63	0	10	0	0
T64	0	20	0	0
T65	1900	0	0	0
T66	2622	0	0	0
T67	286235	0	0	0
T68	4251	0	0	0
T69	2690	0	0	0
T70	10811	0	0	0
T71	811	0	0	0
T72	3579	0	0	0
T73	6498	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	70	0	0
T18	43973	20	0	0
T19	0	10	0	0
T20	0	10	0	0
T63	0	10	0	0
T64	0	20	0	0
T65	1900	0	0	0
T66	2622	0	0	0
T67	286235	0	0	0
T68	4251	0	0	0
T69	2690	0	0	0
T70	10811	0	0	0
T71	811	0	0	0
T72	3579	0	0	0
T73	6498	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	70	0	0
T18	43973	20	0	0
T19	0	10	0	0
T20	0	10	0	0
T63	0	10	0	0
T64	0	20	0	0
T65	1900	0	0	0
T66	2622	0	0	0
T67	286235	0	0	0
T68	4251	0	0	0
T69	2690	0	0	0
T70	10811	0	0	0
T71	811	0	0	0
T72	3579	0	0	0
T73	6498	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	70	0	0
T18	43973	20	0	0
T19	0	10	0	0
T20	0	10	0	0
T63	0	10	0	0
T64	0	20	0	0
T65	1900	0	0	0
T66	2622	0	0	0
T67	286235	0	0	0
T68	4251	0	0	0
T69	2690	0	0	0
T70	10811	0	0	0
T71	811	0	0	0
T72	3579	0	0	0
T73	6498	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	70	0	0
T18	43973	20	0	0
T19	0	10	0	0
T20	0	10	0	0
T63	0	10	0	0
T64	0	20	0	0
T65	1900	0	0	0
T66	2622	0	0	0
T67	286235	0	0	0
T68	4251	0	0	0
T69	2690	0	0	0
T70	10811	0	0	0
T71	811	0	0	0
T72	3579	0	0	0
T73	6498	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	70	0	0
T18	43973	20	0	0
T19	0	10	0	0
T20	0	10	0	0
T63	0	10	0	0
T64	0	20	0	0
T65	1900	0	0	0
T66	2622	0	0	0
T67	286235	0	0	0
T68	4251	0	0	0
T69	2690	0	0	0
T70	10811	0	0	0
T71	811	0	0	0
T72	3579	0	0	0
T73	6498	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	70	0	0
T18	43973	20	0	0
T19	0	10	0	0
T20	0	10	0	0
T63	0	10	0	0
T64	0	20	0	0
T65	1900	0	0	0
T66	2622	0	0	0
T67	286235	0	0	0
T68	4251	0	0	0
T69	2690	0	0	0
T70	10811	0	0	0
T71	811	0	0	0
T72	3579	0	0	0
T73	6498	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	70	0	0
T18	43973	20	0	0
T19	0	10	0	0
T20	0	10	0	0
T63	0	10	0	0
T64	0	20	0	0
T65	1900	0	0	0
T66	2622	0	0	0
T67	286235	0	0	0
T68	4251	0	0	0
T69	2690	0	0	0
T70	10811	0	0	0
T71	811	0	0	0
T72	3579	0	0	0
T73	6498	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	70	0	0
T18	43973	20	0	0
T19	0	10	0	0
T20	0	10	0	0
T63	0	10	0	0
T64	0	20	0	0
T65	1900	0	0	0
T66	2622	0	0	0
T67	286235	0	0	0
T68	4251	0	0	0
T69	2690	0	0	0
T70	10811	0	0	0
T71	811	0	0	0
T72	3579	0	0	0
T73	6498	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	70	0	0
T18	43973	20	0	0
T19	0	10	0	0
T20	0	10	0	0
T63	0	10	0	0
T64	0	20	0	0
T65	1900	0	0	0
T66	2622	0	0	0
T67	286235	0	0	0
T68	4251	0	0	0
T69	2690	0	0	0
T70	10811	0	0	0
T71	811	0	0	0
T72	3579	0	0	0
T73	6498	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	564150	0	312
T1	1655	1593	0	2
T2	1006	937	0	2
T3	6697	299	0	0
T4	755	269	0	0
T7	2773	569	0	0
T8	2470	318	0	0
T11	1943	686	0	2
T24	2468	29	0	0
T25	1663	18	0	0
T26	3252	55	0	0
T40	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	72667	0	411
T4	755	0	0	0
T5	2223	0	0	0
T6	31003	22	0	1
T15	2499	4	0	1
T23	0	915	0	1
T24	2468	15	0	1
T25	1663	3	0	1
T26	3252	70	0	1
T43	0	30	0	1
T47	2159	0	0	0
T48	2458	8	0	1
T49	1089	3	0	1
T62	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	147493	0	0
T4	755	350	0	0
T5	2223	1142	0	0
T6	31003	0	0	0
T9	0	275	0	0
T10	0	602	0	0
T15	2499	0	0	0
T16	0	393	0	0
T17	0	1094	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T33	0	25	0	0
T34	0	1090	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	758	0	0
T81	0	1165	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	564150	0	312
T1	1655	1593	0	2
T2	1006	937	0	2
T3	6697	299	0	0
T4	755	269	0	0
T7	2773	569	0	0
T8	2470	318	0	0
T11	1943	686	0	2
T24	2468	29	0	0
T25	1663	18	0	0
T26	3252	55	0	0
T40	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	4798	0	141
T4	755	0	0	0
T5	2223	0	0	0
T6	31003	0	0	0
T12	0	52	0	1
T13	0	3	0	1
T15	2499	0	0	0
T24	2468	37	0	1
T25	1663	0	0	0
T26	3252	0	0	0
T43	0	24	0	1
T44	0	40	0	1
T46	0	3	0	1
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T82	0	4	0	1
T83	0	4	0	1
T84	0	56	0	1
T85	0	22	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	147493	0	0
T4	755	350	0	0
T5	2223	1142	0	0
T6	31003	0	0	0
T9	0	275	0	0
T10	0	602	0	0
T15	2499	0	0	0
T16	0	393	0	0
T17	0	1094	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T33	0	25	0	0
T34	0	1090	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	758	0	0
T81	0	1165	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	564150	0	312
T1	1655	1593	0	2
T2	1006	937	0	2
T3	6697	299	0	0
T4	755	269	0	0
T7	2773	569	0	0
T8	2470	318	0	0
T11	1943	686	0	2
T24	2468	29	0	0
T25	1663	18	0	0
T26	3252	55	0	0
T40	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	6052	0	127
T3	6697	1071	0	1
T4	755	0	0	0
T5	2223	0	0	0
T7	2773	4	0	1
T8	2470	4	0	1
T11	1943	1	0	0
T12	0	3	0	1
T13	0	0	0	1
T15	2499	0	0	0
T24	2468	0	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T44	0	61	0	1
T45	0	3	0	1
T46	0	45	0	1
T83	0	4	0	0
T85	0	0	0	1
T86	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	147493	0	0
T4	755	350	0	0
T5	2223	1142	0	0
T6	31003	0	0	0
T9	0	275	0	0
T10	0	602	0	0
T15	2499	0	0	0
T16	0	393	0	0
T17	0	1094	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T33	0	25	0	0
T34	0	1090	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	758	0	0
T81	0	1165	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	564150	0	312
T1	1655	1593	0	2
T2	1006	937	0	2
T3	6697	299	0	0
T4	755	269	0	0
T7	2773	569	0	0
T8	2470	318	0	0
T11	1943	686	0	2
T24	2468	29	0	0
T25	1663	18	0	0
T26	3252	55	0	0
T40	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	5737	0	117
T3	6697	25	0	1
T4	755	0	0	0
T5	2223	0	0	0
T7	2773	0	0	0
T8	2470	0	0	0
T11	1943	4	0	0
T12	0	3	0	1
T13	0	20	0	1
T15	2499	0	0	0
T24	2468	0	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T45	0	3	0	1
T46	0	21	0	1
T50	0	7	0	1
T84	0	3	0	1
T86	0	3	0	1
T87	0	4	0	1
T88	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	147493	0	0
T4	755	350	0	0
T5	2223	1142	0	0
T6	31003	0	0	0
T9	0	275	0	0
T10	0	602	0	0
T15	2499	0	0	0
T16	0	393	0	0
T17	0	1094	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T33	0	25	0	0
T34	0	1090	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	758	0	0
T81	0	1165	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	564150	0	312
T1	1655	1593	0	2
T2	1006	937	0	2
T3	6697	299	0	0
T4	755	269	0	0
T7	2773	569	0	0
T8	2470	318	0	0
T11	1943	686	0	2
T24	2468	29	0	0
T25	1663	18	0	0
T26	3252	55	0	0
T40	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	3632	0	110
T3	6697	3	0	1
T4	755	1	0	0
T5	2223	0	0	0
T7	2773	0	0	0
T8	2470	0	0	0
T11	1943	0	0	0
T12	0	17	0	1
T13	0	0	0	1
T15	2499	0	0	0
T24	2468	0	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T30	0	1	0	0
T43	0	7	0	1
T45	0	28	0	1
T46	0	3	0	1
T51	0	4	0	1
T86	0	3	0	1
T89	0	3	0	1
T90	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	147493	0	0
T4	755	350	0	0
T5	2223	1142	0	0
T6	31003	0	0	0
T9	0	275	0	0
T10	0	602	0	0
T15	2499	0	0	0
T16	0	393	0	0
T17	0	1094	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T33	0	25	0	0
T34	0	1090	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	758	0	0
T81	0	1165	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	564150	0	312
T1	1655	1593	0	2
T2	1006	937	0	2
T3	6697	299	0	0
T4	755	269	0	0
T7	2773	569	0	0
T8	2470	318	0	0
T11	1943	686	0	2
T24	2468	29	0	0
T25	1663	18	0	0
T26	3252	55	0	0
T40	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	2609	0	108
T13	0	15	0	1
T21	4268	0	0	0
T27	1127	0	0	0
T43	3261	3	0	1
T44	3649	0	0	0
T45	5066	60	0	1
T46	3027	11	0	1
T51	2454	0	0	0
T52	0	45	0	1
T54	11544	0	0	0
T74	1458	0	0	0
T86	0	3	0	1
T88	0	4	0	0
T89	1427	0	0	0
T91	0	3	0	1
T92	0	4	0	1
T93	0	4	0	1
T94	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	147493	0	0
T4	755	350	0	0
T5	2223	1142	0	0
T6	31003	0	0	0
T9	0	275	0	0
T10	0	602	0	0
T15	2499	0	0	0
T16	0	393	0	0
T17	0	1094	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T33	0	25	0	0
T34	0	1090	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	758	0	0
T81	0	1165	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	564150	0	312
T1	1655	1593	0	2
T2	1006	937	0	2
T3	6697	299	0	0
T4	755	269	0	0
T7	2773	569	0	0
T8	2470	318	0	0
T11	1943	686	0	2
T24	2468	29	0	0
T25	1663	18	0	0
T26	3252	55	0	0
T40	0	0	0	2
T74	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	3754	0	87
T3	6697	3	0	1
T4	755	0	0	0
T5	2223	0	0	0
T7	2773	0	0	0
T8	2470	0	0	0
T11	1943	0	0	0
T12	0	6	0	1
T15	2499	0	0	0
T24	2468	0	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T43	0	8	0	1
T45	0	3	0	1
T47	0	4	0	1
T53	0	15	0	1
T95	0	3	0	1
T96	0	3	0	1
T97	0	10	0	1
T98	0	4	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	196735478	0	0
T1	1655	1595	0	0
T2	1006	939	0	0
T3	6697	6606	0	0
T4	755	596	0	0
T7	2773	2719	0	0
T8	2470	2387	0	0
T11	1943	1890	0	0
T24	2468	2402	0	0
T25	1663	1568	0	0
T26	3252	3191	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196914512	147493	0	0
T4	755	350	0	0
T5	2223	1142	0	0
T6	31003	0	0	0
T9	0	275	0	0
T10	0	602	0	0
T15	2499	0	0	0
T16	0	393	0	0
T17	0	1094	0	0
T25	1663	0	0	0
T26	3252	0	0	0
T33	0	25	0	0
T34	0	1090	0	0
T47	2159	0	0	0
T48	2458	0	0	0
T49	1089	0	0	0
T62	1245	0	0	0
T80	0	758	0	0
T81	0	1165	0	0