Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	197399631	9471386	0	0
boot_gen_cmd_rd_A	197399631	45600	0	0
boot_ins_cmd_rd_A	197399631	51899	0	0
ctrl_rd_A	197399631	45170	0	0
err_code_test_rd_A	197399631	51735	0	0
intr_enable_rd_A	197399631	51936	0	0
max_num_reqs_between_reseeds_rd_A	197399631	46145	0	0
regwen_rd_A	197399631	53436	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197399631	9471386	0	0
T9	1218	0	0	0
T12	4585	0	0	0
T16	950	0	0	0
T40	837111	45678	0	0
T41	464018	162051	0	0
T42	0	154660	0	0
T75	3071	0	0	0
T76	0	223220	0	0
T79	0	88617	0	0
T83	1554	0	0	0
T86	4163	0	0	0
T103	0	104864	0	0
T105	0	213785	0	0
T236	0	247942	0	0
T237	0	174591	0	0
T238	0	682057	0	0
T239	1241	0	0	0
T240	4186	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197399631	45600	0	0
T9	1218	0	0	0
T10	1249	0	0	0
T41	464018	4516	0	0
T42	455971	4698	0	0
T50	4081	0	0	0
T67	0	3135	0	0
T75	3071	0	0	0
T76	0	6503	0	0
T79	0	1503	0	0
T104	2594	0	0	0
T106	2431	0	0	0
T109	1826	0	0	0
T110	2822	0	0	0
T237	0	2742	0	0
T241	0	1436	0	0
T242	0	9364	0	0
T243	0	6467	0	0
T244	0	1672	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197399631	51899	0	0
T9	1218	0	0	0
T10	1249	0	0	0
T41	464018	5431	0	0
T42	455971	5074	0	0
T50	4081	0	0	0
T67	0	3557	0	0
T75	3071	0	0	0
T76	0	7501	0	0
T79	0	1783	0	0
T104	2594	0	0	0
T106	2431	0	0	0
T109	1826	0	0	0
T110	2822	0	0	0
T237	0	2613	0	0
T241	0	1765	0	0
T242	0	10471	0	0
T243	0	7451	0	0
T244	0	2106	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197399631	45170	0	0
T9	1218	0	0	0
T10	1249	0	0	0
T41	464018	4705	0	0
T42	455971	4304	0	0
T50	4081	0	0	0
T67	0	3060	0	0
T75	3071	0	0	0
T76	0	6694	0	0
T79	0	1416	0	0
T104	2594	0	0	0
T106	2431	0	0	0
T109	1826	0	0	0
T110	2822	0	0	0
T193	0	3	0	0
T237	0	2397	0	0
T241	0	1484	0	0
T245	0	1	0	0
T246	0	4	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197399631	51735	0	0
T9	1218	0	0	0
T10	1249	0	0	0
T41	464018	5146	0	0
T42	455971	4820	0	0
T50	4081	0	0	0
T67	0	3423	0	0
T75	3071	0	0	0
T76	0	7568	0	0
T79	0	1612	0	0
T104	2594	0	0	0
T106	2431	0	0	0
T109	1826	0	0	0
T110	2822	0	0	0
T237	0	2874	0	0
T241	0	1870	0	0
T242	0	10837	0	0
T243	0	7491	0	0
T244	0	1854	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197399631	51936	0	0
T6	31003	75	0	0
T21	4268	0	0	0
T23	7450	0	0	0
T27	1127	0	0	0
T41	0	4719	0	0
T42	0	4539	0	0
T43	3261	0	0	0
T44	3649	0	0	0
T45	5066	0	0	0
T51	2454	0	0	0
T62	1245	0	0	0
T74	1458	0	0	0
T76	0	7271	0	0
T79	0	1540	0	0
T237	0	2874	0	0
T241	0	1914	0	0
T247	0	59	0	0
T248	0	71	0	0
T249	0	26	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197399631	46145	0	0
T9	1218	0	0	0
T10	1249	0	0	0
T41	464018	4663	0	0
T42	455971	4505	0	0
T50	4081	0	0	0
T67	0	3117	0	0
T75	3071	0	0	0
T76	0	6610	0	0
T79	0	1405	0	0
T104	2594	0	0	0
T106	2431	0	0	0
T109	1826	0	0	0
T110	2822	0	0	0
T237	0	2355	0	0
T241	0	1621	0	0
T242	0	9607	0	0
T243	0	6367	0	0
T244	0	1459	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197399631	53436	0	0
T9	1218	0	0	0
T10	1249	0	0	0
T41	464018	5210	0	0
T42	455971	5173	0	0
T50	4081	0	0	0
T67	0	3705	0	0
T75	3071	0	0	0
T76	0	7690	0	0
T79	0	1613	0	0
T104	2594	0	0	0
T106	2431	0	0	0
T109	1826	0	0	0
T110	2822	0	0	0
T237	0	2906	0	0
T241	0	1627	0	0
T242	0	10799	0	0
T243	0	7822	0	0
T244	0	1864	0	0