Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	240100224	10793831	0	0
boot_gen_cmd_rd_A	240100224	56743	0	0
boot_ins_cmd_rd_A	240100224	64628	0	0
ctrl_rd_A	240100224	56979	0	0
err_code_test_rd_A	240100224	63677	0	0
intr_enable_rd_A	240100224	62767	0	0
max_num_reqs_between_reseeds_rd_A	240100224	57781	0	0
regwen_rd_A	240100224	65730	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240100224	10793831	0	0
T4	713934	249985	0	0
T5	21424	0	0	0
T6	1970	0	0	0
T33	0	148130	0	0
T34	0	166777	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T38	2250	0	0	0
T41	2085	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T56	0	51295	0	0
T85	0	186928	0	0
T87	0	195073	0	0
T214	0	166938	0	0
T215	0	297770	0	0
T216	0	124407	0	0
T217	0	478215	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240100224	56743	0	0
T4	713934	6926	0	0
T5	21424	0	0	0
T6	1970	0	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T38	2250	0	0	0
T41	2085	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T85	0	5493	0	0
T214	0	2504	0	0
T218	0	4442	0	0
T219	0	2566	0	0
T220	0	1493	0	0
T221	0	12067	0	0
T222	0	7107	0	0
T223	0	1299	0	0
T224	0	5354	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240100224	64628	0	0
T4	713934	8497	0	0
T5	21424	0	0	0
T6	1970	0	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T38	2250	0	0	0
T41	2085	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T85	0	6108	0	0
T214	0	2846	0	0
T218	0	5055	0	0
T219	0	2557	0	0
T220	0	1792	0	0
T221	0	13401	0	0
T222	0	8205	0	0
T223	0	1608	0	0
T224	0	6191	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240100224	56979	0	0
T4	713934	7149	0	0
T5	21424	0	0	0
T6	1970	0	0	0
T14	0	3	0	0
T25	0	3	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T38	2250	0	0	0
T41	2085	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T85	0	5484	0	0
T99	0	7	0	0
T195	0	5	0	0
T214	0	2471	0	0
T225	0	2	0	0
T226	0	1	0	0
T227	0	1	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240100224	63677	0	0
T4	713934	7998	0	0
T5	21424	0	0	0
T6	1970	0	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T38	2250	0	0	0
T41	2085	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T85	0	5853	0	0
T214	0	2868	0	0
T218	0	5260	0	0
T219	0	2532	0	0
T220	0	1572	0	0
T221	0	13355	0	0
T222	0	8338	0	0
T223	0	1590	0	0
T224	0	6176	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240100224	62767	0	0
T4	713934	7460	0	0
T5	21424	0	0	0
T6	1970	0	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T38	2250	0	0	0
T41	2085	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T85	0	5475	0	0
T214	0	2766	0	0
T218	0	4836	0	0
T225	0	41	0	0
T228	0	18	0	0
T229	0	45	0	0
T230	0	13	0	0
T231	0	42	0	0
T232	0	63	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240100224	57781	0	0
T4	713934	7349	0	0
T5	21424	0	0	0
T6	1970	0	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T38	2250	0	0	0
T41	2085	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T85	0	5576	0	0
T214	0	2449	0	0
T218	0	4369	0	0
T219	0	2339	0	0
T220	0	1436	0	0
T221	0	12024	0	0
T222	0	7108	0	0
T223	0	1476	0	0
T224	0	5274	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240100224	65730	0	0
T4	713934	8281	0	0
T5	21424	0	0	0
T6	1970	0	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T38	2250	0	0	0
T41	2085	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T85	0	5519	0	0
T214	0	2920	0	0
T218	0	5089	0	0
T219	0	2854	0	0
T220	0	1768	0	0
T221	0	13673	0	0
T222	0	8562	0	0
T223	0	1448	0	0
T224	0	6045	0	0