Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.19	98.25	93.91	96.97	91.86	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.07	99.92	92.66	82.25	91.86	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T17,T10,T11

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T18,T19
1	0	Covered	T5,T6,T7

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T11,T24,T4	Yes	T11,T24,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T17,T10	Yes	T1,T3,T17	INPUT
tl_i.a_source[7:0]	Yes	Yes	T2,T17,T10	Yes	T2,T17,T10	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T4,T33,T34	Yes	T4,T33,T34	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T17,T10	Yes	T2,T17,T10	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T2,T35,T36	Yes	T2,T35,T36	INPUT
edn_i[2].edn_req	Yes	Yes	T2,T17,T15	Yes	T2,T17,T15	INPUT
edn_i[3].edn_req	Yes	Yes	T15,T36,T20	Yes	T15,T36,T20	INPUT
edn_i[4].edn_req	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
edn_i[5].edn_req	Yes	Yes	T2,T15,T35	Yes	T2,T15,T35	INPUT
edn_i[6].edn_req	Yes	Yes	T2,T10,T15	Yes	T2,T10,T15	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T3,T22	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T2,T35,T36	Yes	T2,T35,T36	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T2,T35,T36	Yes	T2,T35,T36	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T2,T35,T36	Yes	T2,T35,T36	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T2,T17,T38	Yes	T2,T17,T15	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T35,T21,T37	Yes	T17,T38,T35	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T2,T17,T15	Yes	T2,T17,T15	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T15,T36,T20	Yes	T15,T36,T20	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T15,T36,T20	Yes	T15,T36,T20	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T15,T36,T20	Yes	T15,T36,T20	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T36,T39,T40	Yes	T36,T37,T39	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T15,T35,T41	Yes	T15,T35,T36	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T35,T41,T20	Yes	T2,T35,T41	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T2,T15,T35	Yes	T2,T15,T35	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T15,T38,T20	Yes	T15,T38,T20	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T37,T42,T43	Yes	T2,T10,T20	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T2,T10,T15	Yes	T2,T10,T15	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T17,T38,T44	Yes	T17,T38,T44	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T17,T10,T11	Yes	T17,T10,T11	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T5,T45,T6	Yes	T5,T45,T6	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T17,T10,T11	Yes	T17,T10,T11	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T5,T45,T6	Yes	T5,T45,T6	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T33,T34	Yes	T4,T33,T34	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T46,T33	Yes	T4,T46,T33	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	239591687	239405189	0	0
CsrngAppIfOut_A	239591687	239405189	0	0
FpvSecCmCntAlertCheck_A	239591687	130	0	0
FpvSecCmGenCmdFifoRptrCheck_A	239591687	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	239591687	80	0	0
FpvSecCmMainFsmCheck_A	239591687	80	0	0
FpvSecCmRegWeOnehotCheck_A	239591687	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	239591687	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	239591687	80	0	0
IntrEdnCmdReqDoneKnownO_A	239591687	239405189	0	0
TlAReadyKnownO_A	239591687	239405189	0	0
TlDValidKnownO_A	239591687	239405189	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	239591687	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	239591687	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	239591687	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	239591687	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	239591687	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	239591687	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	239591687	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	239591687	581524	0	320
gen_edn_if_asserts[0].EdnDataStable_A	239591687	22080	0	439
gen_edn_if_asserts[0].EdnEndPointOut_A	239591687	239405189	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	239591687	154891	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	239591687	581524	0	320
gen_edn_if_asserts[1].EdnDataStable_A	239591687	4929	0	138
gen_edn_if_asserts[1].EdnEndPointOut_A	239591687	239405189	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	239591687	154891	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	239591687	581524	0	320
gen_edn_if_asserts[2].EdnDataStable_A	239591687	4574	0	129
gen_edn_if_asserts[2].EdnEndPointOut_A	239591687	239405189	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	239591687	154891	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	239591687	581524	0	320
gen_edn_if_asserts[3].EdnDataStable_A	239591687	4335	0	130
gen_edn_if_asserts[3].EdnEndPointOut_A	239591687	239405189	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	239591687	154891	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	239591687	581524	0	320
gen_edn_if_asserts[4].EdnDataStable_A	239591687	5046	0	105
gen_edn_if_asserts[4].EdnEndPointOut_A	239591687	239405189	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	239591687	154891	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	239591687	581524	0	320
gen_edn_if_asserts[5].EdnDataStable_A	239591687	4766	0	95
gen_edn_if_asserts[5].EdnEndPointOut_A	239591687	239405189	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	239591687	154891	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	239591687	581524	0	320
gen_edn_if_asserts[6].EdnDataStable_A	239591687	3183	0	93
gen_edn_if_asserts[6].EdnEndPointOut_A	239591687	239405189	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	239591687	154891	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	239405189	0	0
T1	4895	4799	0	0
T2	2859	2783	0	0
T3	4886	4815	0	0
T10	2433	2348	0	0
T11	3070	2992	0	0
T15	4720	4623	0	0
T17	1909	1857	0	0
T22	2423	2341	0	0
T23	965	913	0	0
T24	2112	2029	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	239405189	0	0
T1	4895	4799	0	0
T2	2859	2783	0	0
T3	4886	4815	0	0
T10	2433	2348	0	0
T11	3070	2992	0	0
T15	4720	4623	0	0
T17	1909	1857	0	0
T22	2423	2341	0	0
T23	965	913	0	0
T24	2112	2029	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	130	0	0
T5	21424	10	0	0
T6	1970	1	0	0
T7	1219	0	0	0
T8	0	1	0	0
T16	0	1	0	0
T18	0	10	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	2954	0	0	0
T53	1297	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	80	0	0
T5	21424	10	0	0
T6	1970	0	0	0
T7	1219	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T54	0	20	0	0
T55	0	20	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	80	0	0
T5	21424	10	0	0
T6	1970	0	0	0
T7	1219	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T54	0	20	0	0
T55	0	20	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	80	0	0
T5	21424	10	0	0
T6	1970	0	0	0
T7	1219	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T54	0	20	0	0
T55	0	20	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	80	0	0
T5	21424	10	0	0
T6	1970	0	0	0
T7	1219	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T54	0	20	0	0
T55	0	20	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	80	0	0
T5	21424	10	0	0
T6	1970	0	0	0
T7	1219	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T54	0	20	0	0
T55	0	20	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	80	0	0
T5	21424	10	0	0
T6	1970	0	0	0
T7	1219	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T54	0	20	0	0
T55	0	20	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	239405189	0	0
T1	4895	4799	0	0
T2	2859	2783	0	0
T3	4886	4815	0	0
T10	2433	2348	0	0
T11	3070	2992	0	0
T15	4720	4623	0	0
T17	1909	1857	0	0
T22	2423	2341	0	0
T23	965	913	0	0
T24	2112	2029	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	239405189	0	0
T1	4895	4799	0	0
T2	2859	2783	0	0
T3	4886	4815	0	0
T10	2433	2348	0	0
T11	3070	2992	0	0
T15	4720	4623	0	0
T17	1909	1857	0	0
T22	2423	2341	0	0
T23	965	913	0	0
T24	2112	2029	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	239405189	0	0
T1	4895	4799	0	0
T2	2859	2783	0	0
T3	4886	4815	0	0
T10	2433	2348	0	0
T11	3070	2992	0	0
T15	4720	4623	0	0
T17	1909	1857	0	0
T22	2423	2341	0	0
T23	965	913	0	0
T24	2112	2029	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	80	0	0
T5	21424	10	0	0
T6	1970	0	0	0
T7	1219	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T54	0	20	0	0
T55	0	20	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	80	0	0
T5	21424	10	0	0
T6	1970	0	0	0
T7	1219	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T54	0	20	0	0
T55	0	20	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	80	0	0
T5	21424	10	0	0
T6	1970	0	0	0
T7	1219	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T54	0	20	0	0
T55	0	20	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	80	0	0
T5	21424	10	0	0
T6	1970	0	0	0
T7	1219	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T54	0	20	0	0
T55	0	20	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	80	0	0
T5	21424	10	0	0
T6	1970	0	0	0
T7	1219	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T54	0	20	0	0
T55	0	20	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	80	0	0
T5	21424	10	0	0
T6	1970	0	0	0
T7	1219	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T54	0	20	0	0
T55	0	20	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	80	0	0
T5	21424	10	0	0
T6	1970	0	0	0
T7	1219	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T54	0	20	0	0
T55	0	20	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	581524	0	320
T1	4895	60	0	0
T2	2859	28	0	0
T3	4886	334	0	0
T4	0	0	0	2
T5	0	0	0	2
T10	2433	246	0	0
T11	3070	367	0	0
T15	4720	258	0	0
T17	1909	182	0	0
T22	2423	12	0	0
T23	965	11	0	0
T24	2112	254	0	0
T33	0	0	0	2
T34	0	0	0	2
T45	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	22080	0	439
T1	4895	53	0	1
T2	2859	3	0	1
T3	4886	15	0	1
T4	0	103	0	0
T10	2433	0	0	0
T11	3070	8	0	1
T15	4720	0	0	0
T17	1909	0	0	0
T22	2423	24	0	1
T23	965	3	0	1
T24	2112	4	0	1
T35	0	61	0	1
T36	0	0	0	1
T52	0	4	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	239405189	0	0
T1	4895	4799	0	0
T2	2859	2783	0	0
T3	4886	4815	0	0
T10	2433	2348	0	0
T11	3070	2992	0	0
T15	4720	4623	0	0
T17	1909	1857	0	0
T22	2423	2341	0	0
T23	965	913	0	0
T24	2112	2029	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	154891	0	0
T5	21424	7455	0	0
T6	1970	1120	0	0
T7	1219	602	0	0
T16	0	619	0	0
T28	0	28	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T46	0	359	0	0
T47	0	678	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T61	0	1167	0	0
T62	0	388	0	0
T63	0	352	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	581524	0	320
T1	4895	60	0	0
T2	2859	28	0	0
T3	4886	334	0	0
T4	0	0	0	2
T5	0	0	0	2
T10	2433	246	0	0
T11	3070	367	0	0
T15	4720	258	0	0
T17	1909	182	0	0
T22	2423	12	0	0
T23	965	11	0	0
T24	2112	254	0	0
T33	0	0	0	2
T34	0	0	0	2
T45	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	4929	0	138
T2	2859	16	0	1
T3	4886	0	0	0
T4	713934	0	0	0
T10	2433	0	0	0
T11	3070	0	0	0
T15	4720	0	0	0
T17	1909	0	0	0
T20	0	42	0	1
T22	2423	0	0	0
T23	965	0	0	0
T24	2112	0	0	0
T35	0	49	0	1
T36	0	63	0	1
T37	0	12	0	1
T40	0	3	0	1
T46	0	1	0	0
T64	0	4	0	1
T65	0	28	0	1
T66	0	4	0	1
T67	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	239405189	0	0
T1	4895	4799	0	0
T2	2859	2783	0	0
T3	4886	4815	0	0
T10	2433	2348	0	0
T11	3070	2992	0	0
T15	4720	4623	0	0
T17	1909	1857	0	0
T22	2423	2341	0	0
T23	965	913	0	0
T24	2112	2029	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	154891	0	0
T5	21424	7455	0	0
T6	1970	1120	0	0
T7	1219	602	0	0
T16	0	619	0	0
T28	0	28	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T46	0	359	0	0
T47	0	678	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T61	0	1167	0	0
T62	0	388	0	0
T63	0	352	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	581524	0	320
T1	4895	60	0	0
T2	2859	28	0	0
T3	4886	334	0	0
T4	0	0	0	2
T5	0	0	0	2
T10	2433	246	0	0
T11	3070	367	0	0
T15	4720	258	0	0
T17	1909	182	0	0
T22	2423	12	0	0
T23	965	11	0	0
T24	2112	254	0	0
T33	0	0	0	2
T34	0	0	0	2
T45	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	4574	0	129
T2	2859	3	0	1
T3	4886	0	0	0
T4	713934	0	0	0
T10	2433	0	0	0
T11	3070	0	0	0
T15	4720	3	0	1
T17	1909	4	0	1
T21	0	32	0	1
T22	2423	0	0	0
T23	965	0	0	0
T24	2112	0	0	0
T35	0	41	0	1
T36	0	3	0	1
T37	0	19	0	1
T38	0	4	0	1
T67	0	15	0	1
T68	0	4	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	239405189	0	0
T1	4895	4799	0	0
T2	2859	2783	0	0
T3	4886	4815	0	0
T10	2433	2348	0	0
T11	3070	2992	0	0
T15	4720	4623	0	0
T17	1909	1857	0	0
T22	2423	2341	0	0
T23	965	913	0	0
T24	2112	2029	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	154891	0	0
T5	21424	7455	0	0
T6	1970	1120	0	0
T7	1219	602	0	0
T16	0	619	0	0
T28	0	28	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T46	0	359	0	0
T47	0	678	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T61	0	1167	0	0
T62	0	388	0	0
T63	0	352	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	581524	0	320
T1	4895	60	0	0
T2	2859	28	0	0
T3	4886	334	0	0
T4	0	0	0	2
T5	0	0	0	2
T10	2433	246	0	0
T11	3070	367	0	0
T15	4720	258	0	0
T17	1909	182	0	0
T22	2423	12	0	0
T23	965	11	0	0
T24	2112	254	0	0
T33	0	0	0	2
T34	0	0	0	2
T45	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	4335	0	130
T4	713934	0	0	0
T5	21424	0	0	0
T15	4720	747	0	1
T16	0	1	0	0
T20	0	22	0	1
T28	0	1	0	0
T35	4235	0	0	0
T36	3205	20	0	1
T37	0	3	0	1
T38	2250	0	0	0
T40	0	19	0	1
T41	2085	0	0	0
T43	0	0	0	1
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T67	0	3	0	1
T69	0	4	0	1
T70	0	3	0	1
T71	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	239405189	0	0
T1	4895	4799	0	0
T2	2859	2783	0	0
T3	4886	4815	0	0
T10	2433	2348	0	0
T11	3070	2992	0	0
T15	4720	4623	0	0
T17	1909	1857	0	0
T22	2423	2341	0	0
T23	965	913	0	0
T24	2112	2029	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	154891	0	0
T5	21424	7455	0	0
T6	1970	1120	0	0
T7	1219	602	0	0
T16	0	619	0	0
T28	0	28	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T46	0	359	0	0
T47	0	678	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T61	0	1167	0	0
T62	0	388	0	0
T63	0	352	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	581524	0	320
T1	4895	60	0	0
T2	2859	28	0	0
T3	4886	334	0	0
T4	0	0	0	2
T5	0	0	0	2
T10	2433	246	0	0
T11	3070	367	0	0
T15	4720	258	0	0
T17	1909	182	0	0
T22	2423	12	0	0
T23	965	11	0	0
T24	2112	254	0	0
T33	0	0	0	2
T34	0	0	0	2
T45	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	5046	0	105
T6	1970	0	0	0
T7	1219	0	0	0
T35	4235	3	0	1
T36	3205	32	0	1
T37	0	3	0	1
T39	0	3	0	1
T40	0	1131	0	1
T41	2085	0	0	0
T42	0	48	0	1
T43	0	3	0	1
T44	1931	0	0	0
T45	1219	0	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T57	0	4	0	0
T71	0	29	0	1
T72	0	4	0	0
T73	2092	0	0	0
T74	0	0	0	1
T75	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	239405189	0	0
T1	4895	4799	0	0
T2	2859	2783	0	0
T3	4886	4815	0	0
T10	2433	2348	0	0
T11	3070	2992	0	0
T15	4720	4623	0	0
T17	1909	1857	0	0
T22	2423	2341	0	0
T23	965	913	0	0
T24	2112	2029	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	154891	0	0
T5	21424	7455	0	0
T6	1970	1120	0	0
T7	1219	602	0	0
T16	0	619	0	0
T28	0	28	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T46	0	359	0	0
T47	0	678	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T61	0	1167	0	0
T62	0	388	0	0
T63	0	352	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	581524	0	320
T1	4895	60	0	0
T2	2859	28	0	0
T3	4886	334	0	0
T4	0	0	0	2
T5	0	0	0	2
T10	2433	246	0	0
T11	3070	367	0	0
T15	4720	258	0	0
T17	1909	182	0	0
T22	2423	12	0	0
T23	965	11	0	0
T24	2112	254	0	0
T33	0	0	0	2
T34	0	0	0	2
T45	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	4766	0	95
T2	2859	3	0	1
T3	4886	0	0	0
T4	713934	0	0	0
T10	2433	0	0	0
T11	3070	0	0	0
T15	4720	3	0	1
T17	1909	0	0	0
T20	0	879	0	1
T22	2423	0	0	0
T23	965	0	0	0
T24	2112	0	0	0
T35	0	30	0	1
T36	0	3	0	1
T37	0	44	0	1
T41	0	32	0	1
T42	0	30	0	1
T67	0	35	0	1
T71	0	15	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	239405189	0	0
T1	4895	4799	0	0
T2	2859	2783	0	0
T3	4886	4815	0	0
T10	2433	2348	0	0
T11	3070	2992	0	0
T15	4720	4623	0	0
T17	1909	1857	0	0
T22	2423	2341	0	0
T23	965	913	0	0
T24	2112	2029	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	154891	0	0
T5	21424	7455	0	0
T6	1970	1120	0	0
T7	1219	602	0	0
T16	0	619	0	0
T28	0	28	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T46	0	359	0	0
T47	0	678	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T61	0	1167	0	0
T62	0	388	0	0
T63	0	352	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	581524	0	320
T1	4895	60	0	0
T2	2859	28	0	0
T3	4886	334	0	0
T4	0	0	0	2
T5	0	0	0	2
T10	2433	246	0	0
T11	3070	367	0	0
T15	4720	258	0	0
T17	1909	182	0	0
T22	2423	12	0	0
T23	965	11	0	0
T24	2112	254	0	0
T33	0	0	0	2
T34	0	0	0	2
T45	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	3183	0	93
T2	2859	3	0	1
T3	4886	0	0	0
T4	713934	0	0	0
T10	2433	4	0	1
T11	3070	0	0	0
T15	4720	3	0	1
T17	1909	0	0	0
T20	0	7	0	1
T22	2423	0	0	0
T23	965	0	0	0
T24	2112	0	0	0
T37	0	52	0	1
T38	0	4	0	0
T42	0	57	0	1
T43	0	57	0	1
T67	0	3	0	1
T76	0	4	0	0
T77	0	0	0	1
T78	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	239405189	0	0
T1	4895	4799	0	0
T2	2859	2783	0	0
T3	4886	4815	0	0
T10	2433	2348	0	0
T11	3070	2992	0	0
T15	4720	4623	0	0
T17	1909	1857	0	0
T22	2423	2341	0	0
T23	965	913	0	0
T24	2112	2029	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	154891	0	0
T5	21424	7455	0	0
T6	1970	1120	0	0
T7	1219	602	0	0
T16	0	619	0	0
T28	0	28	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T46	0	359	0	0
T47	0	678	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T61	0	1167	0	0
T62	0	388	0	0
T63	0	352	0	0