Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T6,T89
1	1	Covered	T1,T2,T17

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T57,T90
1	1	Covered	T3,T17,T10

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T10,T11
1	0	Covered	T5,T6,T7

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T17,T10,T11
1	Covered	T5,T6,T7

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T17,T10,T11
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T17,T10,T11
1	Covered	T5,T6,T7

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T10,T11

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T3,T11,T15
AutoCaptGenCnt	143	Covered	T3,T11,T15
AutoCaptReseedCnt	141	Covered	T3,T11,T15
AutoDispatch	125	Covered	T3,T11,T15
AutoFirstAckWait	119	Covered	T3,T11,T15
AutoLoadIns	69	Covered	T3,T17,T10
AutoSendGenCmd	150	Covered	T3,T11,T15
AutoSendReseedCmd	162	Covered	T3,T11,T15
BootDone	98	Covered	T1,T2,T24
BootGenAckWait	90	Covered	T1,T2,T24
BootInsAckWait	80	Covered	T1,T2,T17
BootLoadGen	85	Covered	T1,T2,T24
BootLoadIns	65	Covered	T1,T2,T17
BootLoadUni	102	Covered	T1,T2,T24
BootPulse	94	Covered	T1,T2,T24
BootUniAckWait	107	Covered	T1,T2,T24
Error	188	Covered	T5,T6,T7
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T17,T10,T11
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T3,T11,T15
AutoAckWait->Error	188	Covered	T94,T95,T96
AutoAckWait->Idle	211	Covered	T57,T76,T72
AutoAckWait->RejectCsrngEntropy	188	Covered	T11,T44,T73
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T3,T11,T15
AutoCaptGenCnt->Error	188	Covered	T9,T97,T98
AutoCaptGenCnt->Idle	211	Covered	T99,T100,T101
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T102,T103,T104
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T3,T11,T15
AutoCaptReseedCnt->Error	188	Not Covered
AutoCaptReseedCnt->Idle	211	Covered	T72,T105,T106
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T107,T108,T109
AutoDispatch->AutoCaptGenCnt	143	Covered	T3,T11,T15
AutoDispatch->AutoCaptReseedCnt	141	Covered	T3,T11,T15
AutoDispatch->Error	188	Covered	T7,T51,T110
AutoDispatch->Idle	138	Covered	T3,T15,T20
AutoDispatch->RejectCsrngEntropy	188	Covered	T111,T112,T113
AutoFirstAckWait->AutoDispatch	125	Covered	T3,T11,T15
AutoFirstAckWait->Error	188	Covered	T8,T114
AutoFirstAckWait->Idle	211	Covered	T115,T116,T117
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T88,T69,T64
AutoLoadIns->AutoFirstAckWait	119	Covered	T3,T11,T15
AutoLoadIns->Error	188	Covered	T118,T119,T120
AutoLoadIns->Idle	211	Covered	T17,T11,T38
AutoLoadIns->RejectCsrngEntropy	188	Covered	T10,T121,T122
AutoSendGenCmd->AutoAckWait	156	Covered	T3,T11,T15
AutoSendGenCmd->Error	188	Covered	T123,T124,T125
AutoSendGenCmd->Idle	211	Covered	T126,T127
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T52,T91,T128
AutoSendReseedCmd->AutoAckWait	168	Covered	T3,T11,T15
AutoSendReseedCmd->Error	188	Covered	T92,T129,T130
AutoSendReseedCmd->Idle	211	Covered	T57,T131,T132
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T38,T133,T134
BootDone->BootLoadUni	102	Covered	T1,T2,T24
BootDone->Error	188	Covered	T6,T135,T136
BootDone->Idle	211	Covered	T137,T138,T139
BootDone->RejectCsrngEntropy	188	Covered	T79,T140,T141
BootGenAckWait->BootPulse	94	Covered	T1,T2,T24
BootGenAckWait->Error	188	Covered	T142,T143,T144
BootGenAckWait->Idle	211	Covered	T39,T47,T62
BootGenAckWait->RejectCsrngEntropy	188	Covered	T145,T146,T147
BootInsAckWait->BootLoadGen	85	Covered	T1,T2,T24
BootInsAckWait->Error	188	Covered	T47,T48,T49
BootInsAckWait->Idle	211	Covered	T6,T61,T63
BootInsAckWait->RejectCsrngEntropy	188	Covered	T17,T24,T148
BootLoadGen->BootGenAckWait	90	Covered	T1,T2,T24
BootLoadGen->Error	188	Covered	T149,T150
BootLoadGen->Idle	211	Covered	T151,T152,T153
BootLoadGen->RejectCsrngEntropy	188	Covered	T154,T155,T156
BootLoadIns->BootInsAckWait	80	Covered	T1,T2,T17
BootLoadIns->Error	188	Covered	T157,T158,T159
BootLoadIns->Idle	211	Covered	T160,T161
BootLoadIns->RejectCsrngEntropy	188	Covered	T162,T163,T164
BootLoadUni->BootUniAckWait	107	Covered	T1,T2,T24
BootLoadUni->Error	188	Covered	T63
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T165,T166,T167
BootPulse->BootDone	98	Covered	T1,T2,T24
BootPulse->Error	188	Covered	T168
BootPulse->Idle	211	Covered	T169,T170,T171
BootPulse->RejectCsrngEntropy	188	Covered	T172,T173,T174
BootUniAckWait->Error	188	Covered	T175,T176
BootUniAckWait->Idle	112	Covered	T1,T2,T24
BootUniAckWait->RejectCsrngEntropy	188	Covered	T89,T177,T178
Idle->AutoLoadIns	69	Covered	T3,T17,T10
Idle->BootLoadIns	65	Covered	T1,T2,T17
Idle->Error	188	Covered	T5,T18,T19
Idle->RejectCsrngEntropy	188	Covered	T24,T38,T73
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T179,T180,T181
RejectCsrngEntropy->Idle	211	Covered	T17,T10,T11
SWPortMode->Error	188	Covered	T5,T46,T16
SWPortMode->Idle	211	Covered	T10,T24,T4
SWPortMode->RejectCsrngEntropy	188	Covered	T17,T10,T11

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T17
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T10
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T17
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T17
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T17
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T24
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T24
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T24
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T24
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T24
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T24,T52,T6
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T24
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T24
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T24
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T11,T15
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T3,T17,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T3,T11,T15
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T11,T15
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T11,T15
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T3,T11,T15
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T3,T15,T20
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T3,T11,T15
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T3,T11,T15
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T15
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T11,T15
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T3,T15,T38
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T15
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T11,T15
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T11,T15
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T10,T11
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T61,T62

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T5,T6,T7
1	0	1	-	Not Covered
1	0	0	-	Covered	T17,T10,T11
0	-	-	1	Covered	T17,T10,T11
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	239591687	150256	0	0
FpvSecCmErrorStEscalate_A	239591687	151431	0	0
u_state_regs_A	239549541	239363043	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	150256	0	0
T5	21424	7195	0	0
T6	1970	1118	0	0
T7	1219	600	0	0
T16	0	617	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T46	0	357	0	0
T47	0	676	0	0
T48	0	1149	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T61	0	1115	0	0
T62	0	336	0	0
T63	0	350	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	151431	0	0
T5	21424	7325	0	0
T6	1970	1119	0	0
T7	1219	601	0	0
T16	0	618	0	0
T35	4235	0	0	0
T36	3205	0	0	0
T41	2085	0	0	0
T44	1931	0	0	0
T45	1219	0	0	0
T46	0	358	0	0
T47	0	677	0	0
T48	0	1150	0	0
T52	2954	0	0	0
T53	1297	0	0	0
T61	0	1116	0	0
T62	0	337	0	0
T63	0	351	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239549541	239363043	0	0
T1	4895	4799	0	0
T2	2859	2783	0	0
T3	4886	4815	0	0
T10	2433	2348	0	0
T11	3070	2992	0	0
T15	4720	4623	0	0
T17	1909	1857	0	0
T22	2423	2341	0	0
T23	965	913	0	0
T24	2112	2029	0	0