Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T17,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T17,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T29,T30
1	1	0	Not Covered
1	1	1	Covered	T3,T17,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T27,T31,T32
1	0	1	Covered	T3,T17,T10
1	1	0	Not Covered
1	1	1	Covered	T3,T11,T15

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T17,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478412414	609865	0	0
DepthKnown_A	479183374	478810378	0	0
RvalidKnown_A	479183374	478810378	0	0
WreadyKnown_A	479183374	478810378	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	478772450	705122	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478412414	609865	0	0
T3	9772	3356	0	0
T4	1427868	0	0	0
T7	0	99	0	0
T10	4866	252	0	0
T11	6140	904	0	0
T15	9440	7213	0	0
T17	3818	283	0	0
T22	4846	0	0	0
T23	1930	0	0	0
T24	4224	0	0	0
T38	4500	993	0	0
T44	0	637	0	0
T52	0	525	0	0
T73	0	674	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479183374	478810378	0	0
T1	9790	9598	0	0
T2	5718	5566	0	0
T3	9772	9630	0	0
T10	4866	4696	0	0
T11	6140	5984	0	0
T15	9440	9246	0	0
T17	3818	3714	0	0
T22	4846	4682	0	0
T23	1930	1826	0	0
T24	4224	4058	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479183374	478810378	0	0
T1	9790	9598	0	0
T2	5718	5566	0	0
T3	9772	9630	0	0
T10	4866	4696	0	0
T11	6140	5984	0	0
T15	9440	9246	0	0
T17	3818	3714	0	0
T22	4846	4682	0	0
T23	1930	1826	0	0
T24	4224	4058	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479183374	478810378	0	0
T1	9790	9598	0	0
T2	5718	5566	0	0
T3	9772	9630	0	0
T10	4866	4696	0	0
T11	6140	5984	0	0
T15	9440	9246	0	0
T17	3818	3714	0	0
T22	4846	4682	0	0
T23	1930	1826	0	0
T24	4224	4058	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	478772450	705122	0	0
T3	9772	3356	0	0
T4	1427868	0	0	0
T6	0	424	0	0
T7	0	1004	0	0
T10	4866	252	0	0
T11	6140	904	0	0
T15	9440	7213	0	0
T17	3818	283	0	0
T22	4846	0	0	0
T23	1930	0	0	0
T24	4224	0	0	0
T38	4500	993	0	0
T44	0	637	0	0
T52	0	525	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T57,T79
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T17,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T30,T80
1	1	0	Not Covered
1	1	1	Covered	T3,T17,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T27,T31
1	0	1	Covered	T3,T17,T10
1	1	0	Not Covered
1	1	1	Covered	T3,T11,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T17,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	239206207	299463	0	0
DepthKnown_A	239591687	239405189	0	0
RvalidKnown_A	239591687	239405189	0	0
WreadyKnown_A	239591687	239405189	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	239386225	346837	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239206207	299463	0	0
T3	4886	1664	0	0
T4	713934	0	0	0
T7	0	43	0	0
T10	2433	127	0	0
T11	3070	447	0	0
T15	4720	3595	0	0
T17	1909	129	0	0
T22	2423	0	0	0
T23	965	0	0	0
T24	2112	0	0	0
T38	2250	376	0	0
T44	0	311	0	0
T52	0	359	0	0
T73	0	340	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	239405189	0	0
T1	4895	4799	0	0
T2	2859	2783	0	0
T3	4886	4815	0	0
T10	2433	2348	0	0
T11	3070	2992	0	0
T15	4720	4623	0	0
T17	1909	1857	0	0
T22	2423	2341	0	0
T23	965	913	0	0
T24	2112	2029	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	239405189	0	0
T1	4895	4799	0	0
T2	2859	2783	0	0
T3	4886	4815	0	0
T10	2433	2348	0	0
T11	3070	2992	0	0
T15	4720	4623	0	0
T17	1909	1857	0	0
T22	2423	2341	0	0
T23	965	913	0	0
T24	2112	2029	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	239405189	0	0
T1	4895	4799	0	0
T2	2859	2783	0	0
T3	4886	4815	0	0
T10	2433	2348	0	0
T11	3070	2992	0	0
T15	4720	4623	0	0
T17	1909	1857	0	0
T22	2423	2341	0	0
T23	965	913	0	0
T24	2112	2029	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	239386225	346837	0	0
T3	4886	1664	0	0
T4	713934	0	0	0
T6	0	213	0	0
T7	0	497	0	0
T10	2433	127	0	0
T11	3070	447	0	0
T15	4720	3595	0	0
T17	1909	129	0	0
T22	2423	0	0	0
T23	965	0	0	0
T24	2112	0	0	0
T38	2250	376	0	0
T44	0	311	0	0
T52	0	359	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T17,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T17,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T29,T81
1	1	0	Not Covered
1	1	1	Covered	T3,T17,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T32,T82
1	0	1	Covered	T3,T17,T10
1	1	0	Not Covered
1	1	1	Covered	T3,T11,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T17,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	239206207	310402	0	0
DepthKnown_A	239591687	239405189	0	0
RvalidKnown_A	239591687	239405189	0	0
WreadyKnown_A	239591687	239405189	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	239386225	358285	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239206207	310402	0	0
T3	4886	1692	0	0
T4	713934	0	0	0
T7	0	56	0	0
T10	2433	125	0	0
T11	3070	457	0	0
T15	4720	3618	0	0
T17	1909	154	0	0
T22	2423	0	0	0
T23	965	0	0	0
T24	2112	0	0	0
T38	2250	617	0	0
T44	0	326	0	0
T52	0	166	0	0
T73	0	334	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	239405189	0	0
T1	4895	4799	0	0
T2	2859	2783	0	0
T3	4886	4815	0	0
T10	2433	2348	0	0
T11	3070	2992	0	0
T15	4720	4623	0	0
T17	1909	1857	0	0
T22	2423	2341	0	0
T23	965	913	0	0
T24	2112	2029	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	239405189	0	0
T1	4895	4799	0	0
T2	2859	2783	0	0
T3	4886	4815	0	0
T10	2433	2348	0	0
T11	3070	2992	0	0
T15	4720	4623	0	0
T17	1909	1857	0	0
T22	2423	2341	0	0
T23	965	913	0	0
T24	2112	2029	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239591687	239405189	0	0
T1	4895	4799	0	0
T2	2859	2783	0	0
T3	4886	4815	0	0
T10	2433	2348	0	0
T11	3070	2992	0	0
T15	4720	4623	0	0
T17	1909	1857	0	0
T22	2423	2341	0	0
T23	965	913	0	0
T24	2112	2029	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	239386225	358285	0	0
T3	4886	1692	0	0
T4	713934	0	0	0
T6	0	211	0	0
T7	0	507	0	0
T10	2433	125	0	0
T11	3070	457	0	0
T15	4720	3618	0	0
T17	1909	154	0	0
T22	2423	0	0	0
T23	965	0	0	0
T24	2112	0	0	0
T38	2250	617	0	0
T44	0	326	0	0
T52	0	166	0	0