Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.20	98.25	93.91	97.02	91.86	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.11	99.92	92.66	82.54	91.86	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T30,T31,T32

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T17,T18
1	0	Covered	T1,T5,T15

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T6	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T4,T41,T42	Yes	T4,T41,T42	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T6	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T6,T22	Yes	T1,T6,T22	INPUT
edn_i[1].edn_req	Yes	Yes	T6,T22,T20	Yes	T6,T22,T20	INPUT
edn_i[2].edn_req	Yes	Yes	T22,T29,T20	Yes	T22,T29,T20	INPUT
edn_i[3].edn_req	Yes	Yes	T2,T20,T21	Yes	T2,T20,T21	INPUT
edn_i[4].edn_req	Yes	Yes	T6,T22,T20	Yes	T6,T22,T20	INPUT
edn_i[5].edn_req	Yes	Yes	T22,T43,T21	Yes	T22,T43,T21	INPUT
edn_i[6].edn_req	Yes	Yes	T22,T21,T44	Yes	T22,T21,T44	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T6,T22,T4	Yes	T6,T22,T4	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T6,T22,T4	Yes	T6,T22,T4	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T6,T22,T4	Yes	T6,T22,T4	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T6,T20,T21	Yes	T6,T22,T20	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T6,T20,T34	Yes	T6,T22,T20	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T6,T22,T20	Yes	T6,T22,T20	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T22,T29,T20	Yes	T22,T29,T20	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T29,T20,T44	Yes	T29,T20,T44	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T22,T29,T20	Yes	T22,T29,T20	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T20,T21,T45	Yes	T2,T20,T21	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T21,T44,T46	Yes	T2,T21,T44	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T2,T20,T21	Yes	T2,T20,T21	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T6,T22,T20	Yes	T6,T22,T20	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T22,T45,T44	Yes	T22,T20,T21	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T6,T22,T20	Yes	T6,T22,T20	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T22,T43,T21	Yes	T22,T43,T21	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T21,T45,T44	Yes	T22,T21,T45	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T22,T43,T21	Yes	T22,T43,T21	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T22,T21,T44	Yes	T22,T21,T44	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T21,T44,T46	Yes	T21,T44,T46	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T22,T21,T44	Yes	T22,T21,T44	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T2,T6,T22	Yes	T2,T6,T22	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T2,T6,T22	Yes	T2,T6,T22	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T2,T6,T22	Yes	T6,T22,T4	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T6,T22,T4	Yes	T6,T22,T4	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T2,T6,T22	Yes	T2,T6,T22	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T31,T32,T47	Yes	T31,T32,T47	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T2,T6,T22	Yes	T2,T6,T22	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T23,T24	Yes	T3,T23,T24	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T3,T23	Yes	T1,T3,T23	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T23,T24	Yes	T3,T23,T24	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T3,T23	Yes	T1,T3,T23	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T41,T42	Yes	T4,T41,T42	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	243501794	243313336	0	0
CsrngAppIfOut_A	243501794	243313336	0	0
FpvSecCmCntAlertCheck_A	243501794	120	0	0
FpvSecCmGenCmdFifoRptrCheck_A	243501794	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	243501794	80	0	0
FpvSecCmMainFsmCheck_A	243501794	80	0	0
FpvSecCmRegWeOnehotCheck_A	243501794	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	243501794	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	243501794	80	0	0
IntrEdnCmdReqDoneKnownO_A	243501794	243313336	0	0
TlAReadyKnownO_A	243501794	243313336	0	0
TlDValidKnownO_A	243501794	243313336	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	243501794	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	243501794	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	243501794	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	243501794	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	243501794	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	243501794	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	243501794	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	243501794	575763	0	320
gen_edn_if_asserts[0].EdnDataStable_A	243501794	74972	0	440
gen_edn_if_asserts[0].EdnEndPointOut_A	243501794	243313336	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	243501794	161884	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	243501794	575763	0	320
gen_edn_if_asserts[1].EdnDataStable_A	243501794	7331	0	137
gen_edn_if_asserts[1].EdnEndPointOut_A	243501794	243313336	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	243501794	161884	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	243501794	575763	0	320
gen_edn_if_asserts[2].EdnDataStable_A	243501794	5999	0	116
gen_edn_if_asserts[2].EdnEndPointOut_A	243501794	243313336	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	243501794	161884	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	243501794	575763	0	320
gen_edn_if_asserts[3].EdnDataStable_A	243501794	2491	0	114
gen_edn_if_asserts[3].EdnEndPointOut_A	243501794	243313336	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	243501794	161884	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	243501794	575763	0	320
gen_edn_if_asserts[4].EdnDataStable_A	243501794	3068	0	106
gen_edn_if_asserts[4].EdnEndPointOut_A	243501794	243313336	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	243501794	161884	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	243501794	575763	0	320
gen_edn_if_asserts[5].EdnDataStable_A	243501794	3872	0	83
gen_edn_if_asserts[5].EdnEndPointOut_A	243501794	243313336	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	243501794	161884	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	243501794	575763	0	320
gen_edn_if_asserts[6].EdnDataStable_A	243501794	2495	0	74
gen_edn_if_asserts[6].EdnEndPointOut_A	243501794	243313336	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	243501794	161884	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	120	0	0
T1	23049	10	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T6	5534	0	0	0
T10	1412	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	80	0	0
T1	23049	10	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T6	5534	0	0	0
T10	1412	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T55	0	10	0	0
T56	0	20	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	80	0	0
T1	23049	10	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T6	5534	0	0	0
T10	1412	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T55	0	10	0	0
T56	0	20	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	80	0	0
T1	23049	10	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T6	5534	0	0	0
T10	1412	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T55	0	10	0	0
T56	0	20	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	80	0	0
T1	23049	10	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T6	5534	0	0	0
T10	1412	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T55	0	10	0	0
T56	0	20	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	80	0	0
T1	23049	10	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T6	5534	0	0	0
T10	1412	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T55	0	10	0	0
T56	0	20	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	80	0	0
T1	23049	10	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T6	5534	0	0	0
T10	1412	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T55	0	10	0	0
T56	0	20	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	80	0	0
T1	23049	10	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T6	5534	0	0	0
T10	1412	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T55	0	10	0	0
T56	0	20	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	80	0	0
T1	23049	10	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T6	5534	0	0	0
T10	1412	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T55	0	10	0	0
T56	0	20	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	80	0	0
T1	23049	10	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T6	5534	0	0	0
T10	1412	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T55	0	10	0	0
T56	0	20	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	80	0	0
T1	23049	10	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T6	5534	0	0	0
T10	1412	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T55	0	10	0	0
T56	0	20	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	80	0	0
T1	23049	10	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T6	5534	0	0	0
T10	1412	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T55	0	10	0	0
T56	0	20	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	80	0	0
T1	23049	10	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T6	5534	0	0	0
T10	1412	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T55	0	10	0	0
T56	0	20	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	80	0	0
T1	23049	10	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T6	5534	0	0	0
T10	1412	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T55	0	10	0	0
T56	0	20	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	575763	0	320
T1	23049	10525	0	2
T2	2869	1383	0	2
T3	1090	1030	0	2
T4	604931	2484	0	2
T6	5534	18	0	0
T10	1412	67	0	0
T22	2545	24	0	0
T23	1012	924	0	2
T24	1679	1627	0	2
T25	1241	18	0	0
T41	0	0	0	2
T42	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	74972	0	440
T4	604931	171	0	0
T5	2058	1	0	0
T6	5534	40	0	1
T10	1412	15	0	1
T11	1394	21	0	1
T19	0	0	0	1
T22	2545	10	0	1
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	3	0	1
T30	0	8	0	1
T31	0	0	0	1
T59	1155	3	0	1
T60	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	161884	0	0
T1	23049	8723	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1070	0	0
T6	5534	0	0	0
T7	0	712	0	0
T8	0	969	0	0
T10	1412	0	0	0
T15	0	671	0	0
T16	0	1119	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T33	0	7	0	0
T34	0	18	0	0
T48	0	1108	0	0
T49	0	388	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	575763	0	320
T1	23049	10525	0	2
T2	2869	1383	0	2
T3	1090	1030	0	2
T4	604931	2484	0	2
T6	5534	18	0	0
T10	1412	67	0	0
T22	2545	24	0	0
T23	1012	924	0	2
T24	1679	1627	0	2
T25	1241	18	0	0
T41	0	0	0	2
T42	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	7331	0	137
T4	604931	0	0	0
T5	2058	0	0	0
T6	5534	15	0	1
T10	1412	0	0	0
T11	1394	0	0	0
T20	0	1118	0	1
T21	0	3	0	1
T22	2545	3	0	1
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T34	0	1	0	0
T44	0	3	0	1
T45	0	3	0	1
T46	0	29	0	1
T47	0	4	0	1
T59	1155	0	0	0
T61	0	3	0	1
T62	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	161884	0	0
T1	23049	8723	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1070	0	0
T6	5534	0	0	0
T7	0	712	0	0
T8	0	969	0	0
T10	1412	0	0	0
T15	0	671	0	0
T16	0	1119	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T33	0	7	0	0
T34	0	18	0	0
T48	0	1108	0	0
T49	0	388	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	575763	0	320
T1	23049	10525	0	2
T2	2869	1383	0	2
T3	1090	1030	0	2
T4	604931	2484	0	2
T6	5534	18	0	0
T10	1412	67	0	0
T22	2545	24	0	0
T23	1012	924	0	2
T24	1679	1627	0	2
T25	1241	18	0	0
T41	0	0	0	2
T42	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	5999	0	116
T4	604931	0	0	0
T5	2058	0	0	0
T10	1412	0	0	0
T11	1394	0	0	0
T12	0	3	0	1
T20	0	27	0	1
T22	2545	3	0	1
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T29	2382	70	0	1
T44	0	52	0	1
T58	0	4	0	0
T59	1155	0	0	0
T61	0	3	0	1
T63	0	4	0	1
T64	0	3	0	1
T65	0	3	0	1
T66	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	161884	0	0
T1	23049	8723	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1070	0	0
T6	5534	0	0	0
T7	0	712	0	0
T8	0	969	0	0
T10	1412	0	0	0
T15	0	671	0	0
T16	0	1119	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T33	0	7	0	0
T34	0	18	0	0
T48	0	1108	0	0
T49	0	388	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	575763	0	320
T1	23049	10525	0	2
T2	2869	1383	0	2
T3	1090	1030	0	2
T4	604931	2484	0	2
T6	5534	18	0	0
T10	1412	67	0	0
T22	2545	24	0	0
T23	1012	924	0	2
T24	1679	1627	0	2
T25	1241	18	0	0
T41	0	0	0	2
T42	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	2491	0	114
T2	2869	4	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T6	5534	0	0	0
T10	1412	0	0	0
T12	0	4	0	1
T20	0	3	0	1
T21	0	231	0	1
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T44	0	26	0	1
T45	0	3	0	1
T46	0	57	0	1
T59	1155	0	0	0
T61	0	24	0	1
T65	0	61	0	1
T66	0	0	0	1
T67	0	3	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	161884	0	0
T1	23049	8723	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1070	0	0
T6	5534	0	0	0
T7	0	712	0	0
T8	0	969	0	0
T10	1412	0	0	0
T15	0	671	0	0
T16	0	1119	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T33	0	7	0	0
T34	0	18	0	0
T48	0	1108	0	0
T49	0	388	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	575763	0	320
T1	23049	10525	0	2
T2	2869	1383	0	2
T3	1090	1030	0	2
T4	604931	2484	0	2
T6	5534	18	0	0
T10	1412	67	0	0
T22	2545	24	0	0
T23	1012	924	0	2
T24	1679	1627	0	2
T25	1241	18	0	0
T41	0	0	0	2
T42	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	3068	0	106
T4	604931	0	0	0
T5	2058	0	0	0
T6	5534	3	0	1
T10	1412	0	0	0
T11	1394	0	0	0
T20	0	3	0	1
T21	0	3	0	1
T22	2545	17	0	1
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T44	0	31	0	1
T45	0	46	0	1
T49	0	1	0	0
T59	1155	0	0	0
T61	0	3	0	1
T64	0	50	0	1
T65	0	0	0	1
T68	0	4	0	0
T69	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	161884	0	0
T1	23049	8723	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1070	0	0
T6	5534	0	0	0
T7	0	712	0	0
T8	0	969	0	0
T10	1412	0	0	0
T15	0	671	0	0
T16	0	1119	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T33	0	7	0	0
T34	0	18	0	0
T48	0	1108	0	0
T49	0	388	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	575763	0	320
T1	23049	10525	0	2
T2	2869	1383	0	2
T3	1090	1030	0	2
T4	604931	2484	0	2
T6	5534	18	0	0
T10	1412	67	0	0
T22	2545	24	0	0
T23	1012	924	0	2
T24	1679	1627	0	2
T25	1241	18	0	0
T41	0	0	0	2
T42	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	3872	0	83
T4	604931	0	0	0
T5	2058	0	0	0
T10	1412	0	0	0
T11	1394	0	0	0
T21	0	58	0	1
T22	2545	3	0	1
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T29	2382	0	0	0
T43	0	4	0	0
T44	0	63	0	1
T45	0	35	0	1
T46	0	3	0	1
T59	1155	0	0	0
T61	0	11	0	1
T64	0	48	0	1
T65	0	3	0	1
T66	0	3	0	1
T70	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	161884	0	0
T1	23049	8723	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1070	0	0
T6	5534	0	0	0
T7	0	712	0	0
T8	0	969	0	0
T10	1412	0	0	0
T15	0	671	0	0
T16	0	1119	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T33	0	7	0	0
T34	0	18	0	0
T48	0	1108	0	0
T49	0	388	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	575763	0	320
T1	23049	10525	0	2
T2	2869	1383	0	2
T3	1090	1030	0	2
T4	604931	2484	0	2
T6	5534	18	0	0
T10	1412	67	0	0
T22	2545	24	0	0
T23	1012	924	0	2
T24	1679	1627	0	2
T25	1241	18	0	0
T41	0	0	0	2
T42	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	2495	0	74
T4	604931	0	0	0
T5	2058	0	0	0
T10	1412	0	0	0
T11	1394	0	0	0
T21	0	35	0	1
T22	2545	3	0	1
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T29	2382	0	0	0
T44	0	59	0	1
T46	0	31	0	1
T59	1155	0	0	0
T64	0	14	0	1
T65	0	3	0	1
T70	0	49	0	1
T71	0	3	0	1
T72	0	4	0	1
T73	0	4	0	0
T74	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	243313336	0	0
T1	23049	12536	0	0
T2	2869	2818	0	0
T3	1090	1032	0	0
T4	604931	604920	0	0
T6	5534	5456	0	0
T10	1412	1323	0	0
T22	2545	2457	0	0
T23	1012	926	0	0
T24	1679	1629	0	0
T25	1241	1147	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243501794	161884	0	0
T1	23049	8723	0	0
T2	2869	0	0	0
T3	1090	0	0	0
T4	604931	0	0	0
T5	0	1070	0	0
T6	5534	0	0	0
T7	0	712	0	0
T8	0	969	0	0
T10	1412	0	0	0
T15	0	671	0	0
T16	0	1119	0	0
T22	2545	0	0	0
T23	1012	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T33	0	7	0	0
T34	0	18	0	0
T48	0	1108	0	0
T49	0	388	0	0