Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	244013820	11266290	0	0
boot_gen_cmd_rd_A	244013820	59744	0	0
boot_ins_cmd_rd_A	244013820	67563	0	0
ctrl_rd_A	244013820	59337	0	0
err_code_test_rd_A	244013820	68807	0	0
intr_enable_rd_A	244013820	64236	0	0
max_num_reqs_between_reseeds_rd_A	244013820	58926	0	0
regwen_rd_A	244013820	67087	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244013820	11266290	0	0
T4	604931	214839	0	0
T5	2058	0	0	0
T10	1412	0	0	0
T11	1394	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T29	2382	0	0	0
T30	2523	0	0	0
T41	0	344441	0	0
T42	0	330003	0	0
T59	1155	0	0	0
T60	2293	0	0	0
T81	0	278425	0	0
T207	0	242442	0	0
T208	0	137292	0	0
T209	0	22987	0	0
T210	0	213549	0	0
T211	0	189748	0	0
T212	0	340301	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244013820	59744	0	0
T4	604931	6049	0	0
T5	2058	0	0	0
T10	1412	0	0	0
T11	1394	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T29	2382	0	0	0
T30	2523	0	0	0
T42	0	9752	0	0
T59	1155	0	0	0
T60	2293	0	0	0
T210	0	6285	0	0
T213	0	4183	0	0
T214	0	2059	0	0
T215	0	5799	0	0
T216	0	3908	0	0
T217	0	4846	0	0
T218	0	693	0	0
T219	0	5446	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244013820	67563	0	0
T4	604931	6277	0	0
T5	2058	0	0	0
T10	1412	0	0	0
T11	1394	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T29	2382	0	0	0
T30	2523	0	0	0
T42	0	11124	0	0
T59	1155	0	0	0
T60	2293	0	0	0
T210	0	6712	0	0
T213	0	4890	0	0
T214	0	1806	0	0
T215	0	6870	0	0
T216	0	4391	0	0
T217	0	6048	0	0
T218	0	772	0	0
T219	0	6140	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244013820	59337	0	0
T4	604931	6061	0	0
T5	2058	0	0	0
T10	1412	0	0	0
T11	1394	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T26	0	5	0	0
T29	2382	0	0	0
T30	2523	0	0	0
T42	0	9717	0	0
T59	1155	0	0	0
T60	2293	0	0	0
T73	0	5	0	0
T210	0	5981	0	0
T213	0	4072	0	0
T214	0	2050	0	0
T215	0	6239	0	0
T220	0	3	0	0
T221	0	2	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244013820	68807	0	0
T4	604931	7081	0	0
T5	2058	0	0	0
T10	1412	0	0	0
T11	1394	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T29	2382	0	0	0
T30	2523	0	0	0
T42	0	11718	0	0
T59	1155	0	0	0
T60	2293	0	0	0
T210	0	7078	0	0
T213	0	4843	0	0
T214	0	2189	0	0
T215	0	6756	0	0
T216	0	4379	0	0
T217	0	5819	0	0
T218	0	769	0	0
T219	0	6110	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244013820	64236	0	0
T4	604931	6947	0	0
T5	2058	0	0	0
T10	1412	0	0	0
T11	1394	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T29	2382	0	0	0
T30	2523	0	0	0
T42	0	10030	0	0
T59	1155	0	0	0
T60	2293	0	0	0
T210	0	6415	0	0
T213	0	4308	0	0
T214	0	2158	0	0
T215	0	6374	0	0
T216	0	3881	0	0
T217	0	5227	0	0
T220	0	10	0	0
T222	0	140	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244013820	58926	0	0
T4	604931	6300	0	0
T5	2058	0	0	0
T10	1412	0	0	0
T11	1394	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T29	2382	0	0	0
T30	2523	0	0	0
T42	0	9404	0	0
T59	1155	0	0	0
T60	2293	0	0	0
T210	0	6361	0	0
T213	0	4096	0	0
T214	0	1905	0	0
T215	0	5515	0	0
T216	0	3950	0	0
T217	0	4558	0	0
T218	0	604	0	0
T219	0	5205	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244013820	67087	0	0
T4	604931	6791	0	0
T5	2058	0	0	0
T10	1412	0	0	0
T11	1394	0	0	0
T24	1679	0	0	0
T25	1241	0	0	0
T29	2382	0	0	0
T30	2523	0	0	0
T42	0	10636	0	0
T59	1155	0	0	0
T60	2293	0	0	0
T210	0	6693	0	0
T213	0	4526	0	0
T214	0	1959	0	0
T215	0	7348	0	0
T216	0	4514	0	0
T217	0	5441	0	0
T218	0	671	0	0
T219	0	5992	0	0