Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.91	98.25	93.91	97.02	90.12	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	93.82	99.92	92.66	82.54	90.12	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T20,T27,T28

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T26,T6,T13

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T9	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	INPUT
tl_i.a_source[7:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T4,T37,T38	Yes	T4,T37,T38	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T3,T9	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T3,T9,T20	Yes	T3,T9,T20	INPUT
edn_i[1].edn_req	Yes	Yes	T2,T18,T39	Yes	T2,T18,T39	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T2,T40	Yes	T1,T2,T40	INPUT
edn_i[3].edn_req	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	INPUT
edn_i[4].edn_req	Yes	Yes	T18,T39,T6	Yes	T18,T39,T6	INPUT
edn_i[5].edn_req	Yes	Yes	T40,T42,T41	Yes	T40,T42,T41	INPUT
edn_i[6].edn_req	Yes	Yes	T19,T40,T28	Yes	T19,T40,T28	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T3,T9,T20	Yes	T3,T9,T20	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T9,T4	Yes	T3,T9,T20	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T3,T9,T20	Yes	T3,T9,T20	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T2,T18,T39	Yes	T2,T18,T39	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T2,T41,T43	Yes	T2,T39,T40	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T2,T18,T39	Yes	T2,T18,T39	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T2,T40	Yes	T1,T2,T40	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T2,T40,T44	Yes	T1,T2,T40	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T2,T40	Yes	T1,T2,T40	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T40,T41,T43	Yes	T39,T40,T41	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T43,T45,T46	Yes	T41,T43,T45	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T39,T6,T44	Yes	T39,T6,T44	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T6,T43,T47	Yes	T39,T6,T44	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T18,T39,T6	Yes	T18,T39,T6	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T40,T42,T41	Yes	T40,T42,T41	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T43,T48,T49	Yes	T40,T42,T41	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T40,T42,T41	Yes	T40,T42,T41	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T40,T28,T41	Yes	T19,T40,T28	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T41,T47,T48	Yes	T19,T41,T47	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T19,T40,T28	Yes	T19,T40,T28	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T2,T3,T9	Yes	T1,T2,T3	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T2,T3,T9	Yes	T1,T2,T3	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T20,T28,T50	Yes	T20,T28,T50	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T20,T21,T51	Yes	T20,T21,T51	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T21,T51,T26	Yes	T21,T51,T26	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T20,T21,T51	Yes	T20,T21,T51	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T21,T51,T26	Yes	T21,T51,T26	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	224193479	224011466	0	0
CsrngAppIfOut_A	224193479	224011466	0	0
FpvSecCmCntAlertCheck_A	224193479	106	0	0
FpvSecCmGenCmdFifoRptrCheck_A	224193479	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	224193479	70	0	0
FpvSecCmMainFsmCheck_A	224193479	70	0	0
FpvSecCmRegWeOnehotCheck_A	224193479	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	224193479	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	224193479	70	0	0
IntrEdnCmdReqDoneKnownO_A	224193479	224011466	0	0
TlAReadyKnownO_A	224193479	224011466	0	0
TlDValidKnownO_A	224193479	224011466	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	224193479	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	224193479	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	224193479	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	224193479	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	224193479	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	224193479	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	224193479	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	224193479	628016	0	316
gen_edn_if_asserts[0].EdnDataStable_A	224193479	70832	0	429
gen_edn_if_asserts[0].EdnEndPointOut_A	224193479	224011466	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	224193479	140482	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	224193479	628016	0	316
gen_edn_if_asserts[1].EdnDataStable_A	224193479	4548	0	147
gen_edn_if_asserts[1].EdnEndPointOut_A	224193479	224011466	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	224193479	140482	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	224193479	628016	0	316
gen_edn_if_asserts[2].EdnDataStable_A	224193479	3066	0	137
gen_edn_if_asserts[2].EdnEndPointOut_A	224193479	224011466	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	224193479	140482	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	224193479	628016	0	316
gen_edn_if_asserts[3].EdnDataStable_A	224193479	7460	0	121
gen_edn_if_asserts[3].EdnEndPointOut_A	224193479	224011466	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	224193479	140482	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	224193479	628016	0	316
gen_edn_if_asserts[4].EdnDataStable_A	224193479	3504	0	123
gen_edn_if_asserts[4].EdnEndPointOut_A	224193479	224011466	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	224193479	140482	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	224193479	628016	0	316
gen_edn_if_asserts[5].EdnDataStable_A	224193479	3636	0	107
gen_edn_if_asserts[5].EdnEndPointOut_A	224193479	224011466	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	224193479	140482	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	224193479	628016	0	316
gen_edn_if_asserts[6].EdnDataStable_A	224193479	3863	0	94
gen_edn_if_asserts[6].EdnEndPointOut_A	224193479	224011466	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	224193479	140482	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	106	0	0
T6	1265	1	0	0
T13	801	1	0	0
T14	0	1	0	0
T15	0	20	0	0
T28	2348	0	0	0
T37	400614	0	0	0
T44	1968	0	0	0
T50	2106	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T61	3608	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	70	0	0
T15	99541	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T56	797	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2721	0	0	0
T65	1152	0	0	0
T66	3958	0	0	0
T67	16950	0	0	0
T68	2523	0	0	0
T69	2870	0	0	0
T70	1508	0	0	0
T71	3916	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	70	0	0
T15	99541	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T56	797	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2721	0	0	0
T65	1152	0	0	0
T66	3958	0	0	0
T67	16950	0	0	0
T68	2523	0	0	0
T69	2870	0	0	0
T70	1508	0	0	0
T71	3916	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	70	0	0
T15	99541	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T56	797	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2721	0	0	0
T65	1152	0	0	0
T66	3958	0	0	0
T67	16950	0	0	0
T68	2523	0	0	0
T69	2870	0	0	0
T70	1508	0	0	0
T71	3916	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	70	0	0
T15	99541	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T56	797	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2721	0	0	0
T65	1152	0	0	0
T66	3958	0	0	0
T67	16950	0	0	0
T68	2523	0	0	0
T69	2870	0	0	0
T70	1508	0	0	0
T71	3916	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	70	0	0
T15	99541	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T56	797	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2721	0	0	0
T65	1152	0	0	0
T66	3958	0	0	0
T67	16950	0	0	0
T68	2523	0	0	0
T69	2870	0	0	0
T70	1508	0	0	0
T71	3916	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	70	0	0
T15	99541	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T56	797	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2721	0	0	0
T65	1152	0	0	0
T66	3958	0	0	0
T67	16950	0	0	0
T68	2523	0	0	0
T69	2870	0	0	0
T70	1508	0	0	0
T71	3916	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	70	0	0
T15	99541	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T56	797	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2721	0	0	0
T65	1152	0	0	0
T66	3958	0	0	0
T67	16950	0	0	0
T68	2523	0	0	0
T69	2870	0	0	0
T70	1508	0	0	0
T71	3916	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	70	0	0
T15	99541	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T56	797	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2721	0	0	0
T65	1152	0	0	0
T66	3958	0	0	0
T67	16950	0	0	0
T68	2523	0	0	0
T69	2870	0	0	0
T70	1508	0	0	0
T71	3916	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	70	0	0
T15	99541	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T56	797	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2721	0	0	0
T65	1152	0	0	0
T66	3958	0	0	0
T67	16950	0	0	0
T68	2523	0	0	0
T69	2870	0	0	0
T70	1508	0	0	0
T71	3916	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	70	0	0
T15	99541	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T56	797	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2721	0	0	0
T65	1152	0	0	0
T66	3958	0	0	0
T67	16950	0	0	0
T68	2523	0	0	0
T69	2870	0	0	0
T70	1508	0	0	0
T71	3916	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	70	0	0
T15	99541	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T56	797	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2721	0	0	0
T65	1152	0	0	0
T66	3958	0	0	0
T67	16950	0	0	0
T68	2523	0	0	0
T69	2870	0	0	0
T70	1508	0	0	0
T71	3916	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	70	0	0
T15	99541	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T56	797	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2721	0	0	0
T65	1152	0	0	0
T66	3958	0	0	0
T67	16950	0	0	0
T68	2523	0	0	0
T69	2870	0	0	0
T70	1508	0	0	0
T71	3916	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	70	0	0
T15	99541	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T56	797	0	0	0
T62	0	10	0	0
T63	0	20	0	0
T64	2721	0	0	0
T65	1152	0	0	0
T66	3958	0	0	0
T67	16950	0	0	0
T68	2523	0	0	0
T69	2870	0	0	0
T70	1508	0	0	0
T71	3916	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	628016	0	316
T1	2995	209	0	0
T2	2130	80	0	0
T3	22812	4592	0	0
T4	238605	905	0	2
T5	12815	854	0	0
T9	4273	351	0	0
T18	1688	550	0	2
T19	0	0	0	2
T20	2217	321	0	0
T21	1428	1357	0	2
T22	993	48	0	0
T37	0	0	0	2
T51	0	0	0	2
T58	0	0	0	2
T61	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	70832	0	429
T3	22812	22	0	1
T4	238605	52	0	0
T5	12815	10	0	0
T9	4273	163	0	1
T18	1688	0	0	0
T20	2217	4	0	1
T21	1428	0	0	0
T22	993	4	0	0
T27	0	4	0	1
T39	0	0	0	1
T51	1122	0	0	0
T72	1658	0	0	0
T74	0	3	0	1
T75	0	12	0	1
T76	0	3	0	1
T77	0	0	0	1
T78	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	140482	0	0
T6	1265	412	0	0
T7	0	1072	0	0
T13	801	376	0	0
T14	0	354	0	0
T26	1846	1072	0	0
T28	2348	0	0	0
T29	0	7	0	0
T31	0	17	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	302	0	0
T80	0	389	0	0
T81	0	492	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	628016	0	316
T1	2995	209	0	0
T2	2130	80	0	0
T3	22812	4592	0	0
T4	238605	905	0	2
T5	12815	854	0	0
T9	4273	351	0	0
T18	1688	550	0	2
T19	0	0	0	2
T20	2217	321	0	0
T21	1428	1357	0	2
T22	993	48	0	0
T37	0	0	0	2
T51	0	0	0	2
T58	0	0	0	2
T61	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	4548	0	147
T2	2130	29	0	1
T3	22812	0	0	0
T4	238605	0	0	0
T5	12815	0	0	0
T9	4273	0	0	0
T18	1688	4	0	0
T20	2217	0	0	0
T21	1428	0	0	0
T22	993	0	0	0
T39	0	3	0	1
T40	0	3	0	1
T41	0	31	0	1
T43	0	62	0	1
T44	0	3	0	1
T47	0	0	0	1
T50	0	4	0	1
T51	1122	0	0	0
T59	0	3	0	1
T82	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	140482	0	0
T6	1265	412	0	0
T7	0	1072	0	0
T13	801	376	0	0
T14	0	354	0	0
T26	1846	1072	0	0
T28	2348	0	0	0
T29	0	7	0	0
T31	0	17	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	302	0	0
T80	0	389	0	0
T81	0	492	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	628016	0	316
T1	2995	209	0	0
T2	2130	80	0	0
T3	22812	4592	0	0
T4	238605	905	0	2
T5	12815	854	0	0
T9	4273	351	0	0
T18	1688	550	0	2
T19	0	0	0	2
T20	2217	321	0	0
T21	1428	1357	0	2
T22	993	48	0	0
T37	0	0	0	2
T51	0	0	0	2
T58	0	0	0	2
T61	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	3066	0	137
T1	2995	15	0	1
T2	2130	15	0	1
T3	22812	0	0	0
T4	238605	0	0	0
T5	12815	0	0	0
T9	4273	0	0	0
T18	1688	0	0	0
T20	2217	0	0	0
T21	1428	0	0	0
T22	993	0	0	0
T40	0	19	0	1
T41	0	3	0	1
T44	0	41	0	1
T47	0	3	0	1
T48	0	3	0	1
T60	0	3	0	1
T83	0	4	0	1
T84	0	9	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	140482	0	0
T6	1265	412	0	0
T7	0	1072	0	0
T13	801	376	0	0
T14	0	354	0	0
T26	1846	1072	0	0
T28	2348	0	0	0
T29	0	7	0	0
T31	0	17	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	302	0	0
T80	0	389	0	0
T81	0	492	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	628016	0	316
T1	2995	209	0	0
T2	2130	80	0	0
T3	22812	4592	0	0
T4	238605	905	0	2
T5	12815	854	0	0
T9	4273	351	0	0
T18	1688	550	0	2
T19	0	0	0	2
T20	2217	321	0	0
T21	1428	1357	0	2
T22	993	48	0	0
T37	0	0	0	2
T51	0	0	0	2
T58	0	0	0	2
T61	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	7460	0	121
T6	1265	0	0	0
T13	801	0	0	0
T26	1846	0	0	0
T28	2348	0	0	0
T29	0	1	0	0
T37	400614	0	0	0
T39	1921	3	0	1
T40	1352	3	0	1
T41	0	3	0	1
T43	0	31	0	1
T45	0	3	0	1
T46	0	747	0	1
T47	0	3	0	1
T48	0	3	0	1
T58	1716	0	0	0
T59	4598	0	0	0
T78	1045	0	0	0
T85	0	1	0	0
T86	0	0	0	1
T87	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	140482	0	0
T6	1265	412	0	0
T7	0	1072	0	0
T13	801	376	0	0
T14	0	354	0	0
T26	1846	1072	0	0
T28	2348	0	0	0
T29	0	7	0	0
T31	0	17	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	302	0	0
T80	0	389	0	0
T81	0	492	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	628016	0	316
T1	2995	209	0	0
T2	2130	80	0	0
T3	22812	4592	0	0
T4	238605	905	0	2
T5	12815	854	0	0
T9	4273	351	0	0
T18	1688	550	0	2
T19	0	0	0	2
T20	2217	321	0	0
T21	1428	1357	0	2
T22	993	48	0	0
T37	0	0	0	2
T51	0	0	0	2
T58	0	0	0	2
T61	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	3504	0	123
T5	12815	0	0	0
T6	0	1	0	0
T18	1688	1	0	0
T21	1428	0	0	0
T22	993	0	0	0
T27	2329	0	0	0
T39	0	15	0	1
T41	0	14	0	1
T43	0	15	0	1
T44	0	3	0	1
T47	0	23	0	1
T48	0	3	0	1
T51	1122	0	0	0
T72	1658	0	0	0
T74	1290	0	0	0
T75	2412	0	0	0
T76	2095	0	0	0
T84	0	15	0	1
T88	0	4	0	0
T89	0	0	0	1
T90	0	0	0	1
T91	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	140482	0	0
T6	1265	412	0	0
T7	0	1072	0	0
T13	801	376	0	0
T14	0	354	0	0
T26	1846	1072	0	0
T28	2348	0	0	0
T29	0	7	0	0
T31	0	17	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	302	0	0
T80	0	389	0	0
T81	0	492	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	628016	0	316
T1	2995	209	0	0
T2	2130	80	0	0
T3	22812	4592	0	0
T4	238605	905	0	2
T5	12815	854	0	0
T9	4273	351	0	0
T18	1688	550	0	2
T19	0	0	0	2
T20	2217	321	0	0
T21	1428	1357	0	2
T22	993	48	0	0
T37	0	0	0	2
T51	0	0	0	2
T58	0	0	0	2
T61	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	3636	0	107
T6	1265	0	0	0
T13	801	0	0	0
T28	2348	0	0	0
T37	400614	0	0	0
T40	1352	3	0	1
T41	0	3	0	1
T42	0	4	0	1
T43	0	16	0	1
T44	1968	0	0	0
T47	0	3	0	1
T48	0	31	0	1
T50	2106	0	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T84	0	3	0	1
T85	0	4	0	0
T87	0	0	0	1
T92	0	4	0	1
T93	0	4	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	140482	0	0
T6	1265	412	0	0
T7	0	1072	0	0
T13	801	376	0	0
T14	0	354	0	0
T26	1846	1072	0	0
T28	2348	0	0	0
T29	0	7	0	0
T31	0	17	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	302	0	0
T80	0	389	0	0
T81	0	492	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	628016	0	316
T1	2995	209	0	0
T2	2130	80	0	0
T3	22812	4592	0	0
T4	238605	905	0	2
T5	12815	854	0	0
T9	4273	351	0	0
T18	1688	550	0	2
T19	0	0	0	2
T20	2217	321	0	0
T21	1428	1357	0	2
T22	993	48	0	0
T37	0	0	0	2
T51	0	0	0	2
T58	0	0	0	2
T61	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	3863	0	94
T6	1265	0	0	0
T13	801	0	0	0
T19	2687	4	0	0
T26	1846	0	0	0
T28	0	4	0	1
T37	400614	0	0	0
T39	1921	0	0	0
T40	1352	3	0	1
T41	0	33	0	1
T43	0	3	0	1
T47	0	50	0	1
T48	0	14	0	1
T58	1716	0	0	0
T77	1720	0	0	0
T78	1045	0	0	0
T84	0	3	0	1
T91	0	0	0	1
T94	0	4	0	1
T95	0	3	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	224011466	0	0
T1	2995	2917	0	0
T2	2130	2056	0	0
T3	22812	21777	0	0
T4	238605	238594	0	0
T5	12815	12370	0	0
T9	4273	4181	0	0
T18	1688	1621	0	0
T20	2217	2133	0	0
T21	1428	1359	0	0
T22	993	932	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224193479	140482	0	0
T6	1265	412	0	0
T7	0	1072	0	0
T13	801	376	0	0
T14	0	354	0	0
T26	1846	1072	0	0
T28	2348	0	0	0
T29	0	7	0	0
T31	0	17	0	0
T37	400614	0	0	0
T40	1352	0	0	0
T58	1716	0	0	0
T59	4598	0	0	0
T60	889	0	0	0
T78	1045	0	0	0
T79	0	302	0	0
T80	0	389	0	0
T81	0	492	0	0