Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	224719323	10388290	0	0
boot_gen_cmd_rd_A	224719323	41497	0	0
boot_ins_cmd_rd_A	224719323	46782	0	0
ctrl_rd_A	224719323	41688	0	0
err_code_test_rd_A	224719323	46763	0	0
intr_enable_rd_A	224719323	47555	0	0
max_num_reqs_between_reseeds_rd_A	224719323	41793	0	0
regwen_rd_A	224719323	47783	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224719323	10388290	0	0
T4	238605	130246	0	0
T5	12815	0	0	0
T18	1688	0	0	0
T21	1428	0	0	0
T22	993	0	0	0
T37	0	223043	0	0
T38	0	181310	0	0
T51	1122	0	0	0
T72	1658	0	0	0
T74	1290	0	0	0
T75	2412	0	0	0
T76	2095	0	0	0
T102	0	145774	0	0
T218	0	266231	0	0
T219	0	279909	0	0
T220	0	173558	0	0
T221	0	132207	0	0
T222	0	554796	0	0
T223	0	339077	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224719323	41497	0	0
T10	2161	0	0	0
T164	800	0	0	0
T172	2427	0	0	0
T185	1209	0	0	0
T220	472387	2829	0	0
T221	0	3871	0	0
T224	0	5333	0	0
T225	0	2139	0	0
T226	0	7261	0	0
T227	0	1120	0	0
T228	0	2431	0	0
T229	0	5763	0	0
T230	0	7153	0	0
T231	0	1474	0	0
T232	4126	0	0	0
T233	1895	0	0	0
T234	2983	0	0	0
T235	4544	0	0	0
T236	18355	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224719323	46782	0	0
T10	2161	0	0	0
T164	800	0	0	0
T172	2427	0	0	0
T185	1209	0	0	0
T220	472387	3004	0	0
T221	0	4584	0	0
T224	0	6196	0	0
T225	0	2255	0	0
T226	0	7982	0	0
T227	0	1151	0	0
T228	0	2717	0	0
T229	0	6591	0	0
T230	0	8309	0	0
T231	0	1660	0	0
T232	4126	0	0	0
T233	1895	0	0	0
T234	2983	0	0	0
T235	4544	0	0	0
T236	18355	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224719323	41688	0	0
T14	740	0	0	0
T38	307399	0	0	0
T41	2593	7	0	0
T43	2959	0	0	0
T45	796	0	0	0
T47	5758	0	0	0
T67	0	5	0	0
T73	17227	0	0	0
T79	597	0	0	0
T108	1777	0	0	0
T113	0	1	0	0
T175	0	6	0	0
T220	0	2565	0	0
T221	0	4054	0	0
T224	0	5701	0	0
T236	0	9	0	0
T237	0	6	0	0
T238	0	4	0	0
T239	2905	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224719323	46763	0	0
T10	2161	0	0	0
T164	800	0	0	0
T172	2427	0	0	0
T185	1209	0	0	0
T220	472387	3014	0	0
T221	0	4312	0	0
T224	0	6478	0	0
T225	0	2376	0	0
T226	0	8141	0	0
T227	0	1045	0	0
T228	0	2739	0	0
T229	0	6458	0	0
T230	0	8217	0	0
T231	0	1811	0	0
T232	4126	0	0	0
T233	1895	0	0	0
T234	2983	0	0	0
T235	4544	0	0	0
T236	18355	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224719323	47555	0	0
T3	22812	56	0	0
T4	238605	0	0	0
T5	12815	0	0	0
T9	4273	0	0	0
T18	1688	0	0	0
T20	2217	0	0	0
T21	1428	0	0	0
T22	993	0	0	0
T51	1122	0	0	0
T67	0	57	0	0
T72	1658	0	0	0
T220	0	3213	0	0
T221	0	4365	0	0
T224	0	6350	0	0
T225	0	2257	0	0
T236	0	108	0	0
T240	0	78	0	0
T241	0	9	0	0
T242	0	80	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224719323	41793	0	0
T10	2161	0	0	0
T164	800	0	0	0
T172	2427	0	0	0
T185	1209	0	0	0
T220	472387	2669	0	0
T221	0	3592	0	0
T224	0	5893	0	0
T225	0	2172	0	0
T226	0	7040	0	0
T227	0	1102	0	0
T228	0	2195	0	0
T229	0	5473	0	0
T230	0	7123	0	0
T231	0	1628	0	0
T232	4126	0	0	0
T233	1895	0	0	0
T234	2983	0	0	0
T235	4544	0	0	0
T236	18355	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224719323	47783	0	0
T10	2161	0	0	0
T164	800	0	0	0
T172	2427	0	0	0
T185	1209	0	0	0
T220	472387	3077	0	0
T221	0	4545	0	0
T224	0	6647	0	0
T225	0	2210	0	0
T226	0	7941	0	0
T227	0	1113	0	0
T228	0	2932	0	0
T229	0	6457	0	0
T230	0	8254	0	0
T231	0	1648	0	0
T232	4126	0	0	0
T233	1895	0	0	0
T234	2983	0	0	0
T235	4544	0	0	0
T236	18355	0	0	0