Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.11	98.25	93.97	97.02	91.28	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.03	99.92	92.75	82.54	91.28	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T23

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T19
1	0	Covered	T2,T16,T30

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T23	Yes	T1,T3,T23	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T23	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T34,T35,T36	Yes	T34,T35,T36	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T3,T9,T24	Yes	T3,T9,T24	INPUT
edn_i[1].edn_req	Yes	Yes	T23,T37,T12	Yes	T23,T37,T12	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	INPUT
edn_i[3].edn_req	Yes	Yes	T3,T37,T12	Yes	T3,T37,T12	INPUT
edn_i[4].edn_req	Yes	Yes	T10,T22,T11	Yes	T10,T22,T11	INPUT
edn_i[5].edn_req	Yes	Yes	T10,T37,T38	Yes	T10,T37,T38	INPUT
edn_i[6].edn_req	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T3,T9,T24	Yes	T3,T9,T24	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T9,T5,T16	Yes	T3,T9,T5	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T3,T9,T24	Yes	T3,T9,T24	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T23,T37,T12	Yes	T23,T37,T12	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T12,T20,T39	Yes	T37,T12,T20	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T23,T37,T12	Yes	T23,T37,T12	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T10,T11,T6	Yes	T9,T10,T11	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T3,T37,T12	Yes	T3,T37,T12	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T37,T40,T41	Yes	T37,T12,T42	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T3,T37,T12	Yes	T3,T37,T12	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T10,T22,T11	Yes	T10,T22,T11	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T11,T12,T40	Yes	T10,T11,T43	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T10,T22,T11	Yes	T10,T22,T11	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T10,T37,T38	Yes	T10,T37,T38	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T38,T44,T45	Yes	T10,T37,T38	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T10,T37,T38	Yes	T10,T37,T38	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T9,T10,T12	Yes	T1,T9,T10	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T1,T9,T10	Yes	T1,T9,T10	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T9,T5	Yes	T9,T5,T10	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T9,T5,T10	Yes	T1,T3,T9	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T3,T23	Yes	T1,T3,T23	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T23,T22,T46	Yes	T23,T22,T46	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T3,T23	Yes	T1,T3,T23	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T16,T30	Yes	T2,T16,T30	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T3,T23	Yes	T1,T3,T23	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T16,T30	Yes	T2,T16,T30	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T5,T47	Yes	T4,T5,T47	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	211926576	211734086	0	0
CsrngAppIfOut_A	211926576	211734086	0	0
FpvSecCmCntAlertCheck_A	211926576	123	0	0
FpvSecCmGenCmdFifoRptrCheck_A	211926576	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	211926576	80	0	0
FpvSecCmMainFsmCheck_A	211926576	80	0	0
FpvSecCmRegWeOnehotCheck_A	211926576	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	211926576	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	211926576	80	0	0
IntrEdnCmdReqDoneKnownO_A	211926576	211734086	0	0
TlAReadyKnownO_A	211926576	211734086	0	0
TlDValidKnownO_A	211926576	211734086	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	211926576	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	211926576	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	211926576	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	211926576	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	211926576	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	211926576	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	211926576	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	211926576	622894	0	340
gen_edn_if_asserts[0].EdnDataStable_A	211926576	69143	0	398
gen_edn_if_asserts[0].EdnEndPointOut_A	211926576	211734086	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	211926576	157151	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	211926576	622894	0	340
gen_edn_if_asserts[1].EdnDataStable_A	211926576	5281	0	130
gen_edn_if_asserts[1].EdnEndPointOut_A	211926576	211734086	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	211926576	157151	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	211926576	622894	0	340
gen_edn_if_asserts[2].EdnDataStable_A	211926576	2690	0	125
gen_edn_if_asserts[2].EdnEndPointOut_A	211926576	211734086	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	211926576	157151	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	211926576	622894	0	340
gen_edn_if_asserts[3].EdnDataStable_A	211926576	6343	0	114
gen_edn_if_asserts[3].EdnEndPointOut_A	211926576	211734086	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	211926576	157151	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	211926576	622894	0	340
gen_edn_if_asserts[4].EdnDataStable_A	211926576	3456	0	100
gen_edn_if_asserts[4].EdnEndPointOut_A	211926576	211734086	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	211926576	157151	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	211926576	622894	0	340
gen_edn_if_asserts[5].EdnDataStable_A	211926576	3404	0	92
gen_edn_if_asserts[5].EdnEndPointOut_A	211926576	211734086	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	211926576	157151	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	211926576	622894	0	340
gen_edn_if_asserts[6].EdnDataStable_A	211926576	6258	0	86
gen_edn_if_asserts[6].EdnEndPointOut_A	211926576	211734086	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	211926576	157151	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	123	0	0
T6	0	1	0	0
T14	1043	1	0	0
T15	0	1	0	0
T34	429449	0	0	0
T35	202563	0	0	0
T46	2306	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	1416	0	0	0
T56	1963	0	0	0
T57	1244	0	0	0
T58	923	0	0	0
T59	3899	0	0	0
T60	2399	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	80	0	0
T17	59415	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T25	1408	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	2084	0	0	0
T64	755	0	0	0
T65	1091	0	0	0
T66	912	0	0	0
T67	2239	0	0	0
T68	4112	0	0	0
T69	1614	0	0	0
T70	1944	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	80	0	0
T17	59415	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T25	1408	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	2084	0	0	0
T64	755	0	0	0
T65	1091	0	0	0
T66	912	0	0	0
T67	2239	0	0	0
T68	4112	0	0	0
T69	1614	0	0	0
T70	1944	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	80	0	0
T17	59415	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T25	1408	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	2084	0	0	0
T64	755	0	0	0
T65	1091	0	0	0
T66	912	0	0	0
T67	2239	0	0	0
T68	4112	0	0	0
T69	1614	0	0	0
T70	1944	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	80	0	0
T17	59415	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T25	1408	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	2084	0	0	0
T64	755	0	0	0
T65	1091	0	0	0
T66	912	0	0	0
T67	2239	0	0	0
T68	4112	0	0	0
T69	1614	0	0	0
T70	1944	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	80	0	0
T17	59415	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T25	1408	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	2084	0	0	0
T64	755	0	0	0
T65	1091	0	0	0
T66	912	0	0	0
T67	2239	0	0	0
T68	4112	0	0	0
T69	1614	0	0	0
T70	1944	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	80	0	0
T17	59415	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T25	1408	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	2084	0	0	0
T64	755	0	0	0
T65	1091	0	0	0
T66	912	0	0	0
T67	2239	0	0	0
T68	4112	0	0	0
T69	1614	0	0	0
T70	1944	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	80	0	0
T17	59415	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T25	1408	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	2084	0	0	0
T64	755	0	0	0
T65	1091	0	0	0
T66	912	0	0	0
T67	2239	0	0	0
T68	4112	0	0	0
T69	1614	0	0	0
T70	1944	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	80	0	0
T17	59415	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T25	1408	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	2084	0	0	0
T64	755	0	0	0
T65	1091	0	0	0
T66	912	0	0	0
T67	2239	0	0	0
T68	4112	0	0	0
T69	1614	0	0	0
T70	1944	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	80	0	0
T17	59415	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T25	1408	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	2084	0	0	0
T64	755	0	0	0
T65	1091	0	0	0
T66	912	0	0	0
T67	2239	0	0	0
T68	4112	0	0	0
T69	1614	0	0	0
T70	1944	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	80	0	0
T17	59415	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T25	1408	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	2084	0	0	0
T64	755	0	0	0
T65	1091	0	0	0
T66	912	0	0	0
T67	2239	0	0	0
T68	4112	0	0	0
T69	1614	0	0	0
T70	1944	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	80	0	0
T17	59415	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T25	1408	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	2084	0	0	0
T64	755	0	0	0
T65	1091	0	0	0
T66	912	0	0	0
T67	2239	0	0	0
T68	4112	0	0	0
T69	1614	0	0	0
T70	1944	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	80	0	0
T17	59415	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T25	1408	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	2084	0	0	0
T64	755	0	0	0
T65	1091	0	0	0
T66	912	0	0	0
T67	2239	0	0	0
T68	4112	0	0	0
T69	1614	0	0	0
T70	1944	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	80	0	0
T17	59415	20	0	0
T18	0	10	0	0
T19	0	10	0	0
T25	1408	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	2084	0	0	0
T64	755	0	0	0
T65	1091	0	0	0
T66	912	0	0	0
T67	2239	0	0	0
T68	4112	0	0	0
T69	1614	0	0	0
T70	1944	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	622894	0	340
T1	1765	241	0	0
T2	625	234	0	0
T3	2635	198	0	0
T4	1774	1640	0	2
T5	34679	4142	0	2
T9	6508	49	0	0
T10	4590	111	0	0
T16	2166	1038	0	0
T21	0	0	0	2
T23	2140	152	0	0
T24	1621	16	0	0
T34	0	0	0	2
T35	0	0	0	2
T43	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	69143	0	398
T3	2635	4	0	1
T4	1774	0	0	0
T5	34679	23	0	0
T9	6508	1203	0	1
T10	4590	44	0	1
T16	2166	1	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	3	0	1
T37	1479	0	0	0
T38	0	3	0	1
T75	0	3	0	1
T76	0	3	0	1
T77	0	3	0	1
T78	0	0	0	1
T79	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	157151	0	0
T2	625	302	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1074	0	0
T7	0	362	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	604	0	0
T16	2166	40	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T27	0	7	0	0
T30	0	627	0	0
T31	0	393	0	0
T58	0	386	0	0
T80	0	532	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	622894	0	340
T1	1765	241	0	0
T2	625	234	0	0
T3	2635	198	0	0
T4	1774	1640	0	2
T5	34679	4142	0	2
T9	6508	49	0	0
T10	4590	111	0	0
T16	2166	1038	0	0
T21	0	0	0	2
T23	2140	152	0	0
T24	1621	16	0	0
T34	0	0	0	2
T35	0	0	0	2
T43	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	5281	0	130
T5	34679	0	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T11	1802	0	0	0
T12	0	58	0	1
T13	0	3	0	1
T16	2166	0	0	0
T20	0	291	0	1
T22	1727	0	0	0
T23	2140	4	0	1
T24	1621	0	0	0
T37	1479	3	0	1
T39	0	8	0	1
T41	0	0	0	1
T43	3101	0	0	0
T58	0	1	0	0
T81	0	3	0	1
T82	0	24	0	1
T83	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	157151	0	0
T2	625	302	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1074	0	0
T7	0	362	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	604	0	0
T16	2166	40	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T27	0	7	0	0
T30	0	627	0	0
T31	0	393	0	0
T58	0	386	0	0
T80	0	532	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	622894	0	340
T1	1765	241	0	0
T2	625	234	0	0
T3	2635	198	0	0
T4	1774	1640	0	2
T5	34679	4142	0	2
T9	6508	49	0	0
T10	4590	111	0	0
T16	2166	1038	0	0
T21	0	0	0	2
T23	2140	152	0	0
T24	1621	16	0	0
T34	0	0	0	2
T35	0	0	0	2
T43	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	2690	0	125
T1	1765	4	0	0
T2	625	0	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T9	6508	3	0	1
T10	4590	15	0	1
T11	0	28	0	1
T13	0	35	0	1
T16	2166	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T41	0	0	0	1
T42	0	3	0	1
T83	0	3	0	1
T84	0	4	0	1
T85	0	4	0	0
T86	0	3	0	1
T87	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	157151	0	0
T2	625	302	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1074	0	0
T7	0	362	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	604	0	0
T16	2166	40	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T27	0	7	0	0
T30	0	627	0	0
T31	0	393	0	0
T58	0	386	0	0
T80	0	532	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	622894	0	340
T1	1765	241	0	0
T2	625	234	0	0
T3	2635	198	0	0
T4	1774	1640	0	2
T5	34679	4142	0	2
T9	6508	49	0	0
T10	4590	111	0	0
T16	2166	1038	0	0
T21	0	0	0	2
T23	2140	152	0	0
T24	1621	16	0	0
T34	0	0	0	2
T35	0	0	0	2
T43	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	6343	0	114
T3	2635	4	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T12	0	3	0	1
T16	2166	0	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T27	0	1	0	0
T37	1479	53	0	1
T40	0	11	0	1
T41	0	47	0	1
T42	0	3	0	1
T44	0	0	0	1
T83	0	3	0	1
T84	0	4	0	0
T87	0	22	0	1
T88	0	0	0	1
T89	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	157151	0	0
T2	625	302	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1074	0	0
T7	0	362	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	604	0	0
T16	2166	40	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T27	0	7	0	0
T30	0	627	0	0
T31	0	393	0	0
T58	0	386	0	0
T80	0	532	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	622894	0	340
T1	1765	241	0	0
T2	625	234	0	0
T3	2635	198	0	0
T4	1774	1640	0	2
T5	34679	4142	0	2
T9	6508	49	0	0
T10	4590	111	0	0
T16	2166	1038	0	0
T21	0	0	0	2
T23	2140	152	0	0
T24	1621	16	0	0
T34	0	0	0	2
T35	0	0	0	2
T43	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	3456	0	100
T10	4590	3	0	1
T11	1802	39	0	1
T12	3165	50	0	1
T13	0	0	0	1
T22	1727	4	0	1
T30	1123	0	0	0
T31	774	0	0	0
T37	1479	0	0	0
T38	3744	3	0	1
T40	0	0	0	1
T42	0	14	0	1
T43	3101	4	0	0
T55	0	3	0	1
T75	3824	0	0	0
T83	0	3	0	1
T90	0	1	0	0

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	157151	0	0
T2	625	302	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1074	0	0
T7	0	362	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	604	0	0
T16	2166	40	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T27	0	7	0	0
T30	0	627	0	0
T31	0	393	0	0
T58	0	386	0	0
T80	0	532	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	622894	0	340
T1	1765	241	0	0
T2	625	234	0	0
T3	2635	198	0	0
T4	1774	1640	0	2
T5	34679	4142	0	2
T9	6508	49	0	0
T10	4590	111	0	0
T16	2166	1038	0	0
T21	0	0	0	2
T23	2140	152	0	0
T24	1621	16	0	0
T34	0	0	0	2
T35	0	0	0	2
T43	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	3404	0	92
T10	4590	3	0	1
T11	1802	0	0	0
T12	3165	0	0	0
T13	0	3	0	1
T21	0	4	0	0
T22	1727	0	0	0
T30	1123	0	0	0
T31	774	0	0	0
T37	1479	18	0	1
T38	3744	58	0	1
T41	0	3	0	1
T43	3101	0	0	0
T44	0	0	0	1
T75	3824	0	0	0
T91	0	4	0	0
T92	0	3	0	1
T93	0	3	0	1
T94	0	4	0	1
T95	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	157151	0	0
T2	625	302	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1074	0	0
T7	0	362	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	604	0	0
T16	2166	40	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T27	0	7	0	0
T30	0	627	0	0
T31	0	393	0	0
T58	0	386	0	0
T80	0	532	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	622894	0	340
T1	1765	241	0	0
T2	625	234	0	0
T3	2635	198	0	0
T4	1774	1640	0	2
T5	34679	4142	0	2
T9	6508	49	0	0
T10	4590	111	0	0
T16	2166	1038	0	0
T21	0	0	0	2
T23	2140	152	0	0
T24	1621	16	0	0
T34	0	0	0	2
T35	0	0	0	2
T43	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	6258	0	86
T1	1765	4	0	1
T2	625	0	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T7	0	1	0	0
T9	6508	43	0	1
T10	4590	123	0	1
T12	0	48	0	1
T13	0	0	0	1
T16	2166	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T42	0	40	0	1
T60	0	4	0	0
T93	0	36	0	1
T95	0	0	0	1
T96	0	4	0	0
T97	0	846	0	1
T98	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	211734086	0	0
T1	1765	1680	0	0
T2	625	443	0	0
T3	2635	2550	0	0
T4	1774	1661	0	0
T5	34679	33977	0	0
T9	6508	6422	0	0
T10	4590	4524	0	0
T16	2166	2009	0	0
T23	2140	2064	0	0
T24	1621	1567	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211926576	157151	0	0
T2	625	302	0	0
T3	2635	0	0	0
T4	1774	0	0	0
T5	34679	0	0	0
T6	0	1074	0	0
T7	0	362	0	0
T9	6508	0	0	0
T10	4590	0	0	0
T14	0	604	0	0
T16	2166	40	0	0
T22	1727	0	0	0
T23	2140	0	0	0
T24	1621	0	0	0
T27	0	7	0	0
T30	0	627	0	0
T31	0	393	0	0
T58	0	386	0	0
T80	0	532	0	0