Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	212434727	9303618	0	0
boot_gen_cmd_rd_A	212434727	82378	0	0
boot_ins_cmd_rd_A	212434727	94709	0	0
ctrl_rd_A	212434727	82769	0	0
err_code_test_rd_A	212434727	96241	0	0
intr_enable_rd_A	212434727	93361	0	0
max_num_reqs_between_reseeds_rd_A	212434727	85261	0	0
regwen_rd_A	212434727	95079	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212434727	9303618	0	0
T20	2928	0	0	0
T21	1506	0	0	0
T34	429449	145046	0	0
T35	202563	81385	0	0
T36	0	57455	0	0
T46	2306	0	0	0
T60	2399	0	0	0
T73	6953	0	0	0
T91	1118	0	0	0
T92	1303	0	0	0
T100	1645	0	0	0
T109	0	377654	0	0
T112	0	66148	0	0
T238	0	384169	0	0
T239	0	306917	0	0
T240	0	149402	0	0
T241	0	319344	0	0
T242	0	257420	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212434727	82378	0	0
T20	2928	0	0	0
T21	1506	0	0	0
T34	429449	4136	0	0
T35	202563	0	0	0
T36	0	1655	0	0
T46	2306	0	0	0
T60	2399	0	0	0
T73	6953	0	0	0
T91	1118	0	0	0
T92	1303	0	0	0
T100	1645	0	0	0
T240	0	4185	0	0
T241	0	9546	0	0
T242	0	3628	0	0
T243	0	3543	0	0
T244	0	1649	0	0
T245	0	5218	0	0
T246	0	1099	0	0
T247	0	1363	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212434727	94709	0	0
T20	2928	0	0	0
T21	1506	0	0	0
T34	429449	5064	0	0
T35	202563	0	0	0
T36	0	1880	0	0
T46	2306	0	0	0
T60	2399	0	0	0
T73	6953	0	0	0
T91	1118	0	0	0
T92	1303	0	0	0
T100	1645	0	0	0
T240	0	4631	0	0
T241	0	10851	0	0
T242	0	4417	0	0
T243	0	4030	0	0
T244	0	1716	0	0
T245	0	6281	0	0
T246	0	1263	0	0
T247	0	1640	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212434727	82769	0	0
T12	3165	0	0	0
T28	0	5	0	0
T30	1123	0	0	0
T31	774	0	0	0
T34	0	4151	0	0
T36	0	1605	0	0
T38	3744	0	0	0
T43	3101	4	0	0
T47	6755	0	0	0
T56	0	3	0	0
T75	3824	0	0	0
T76	1082	0	0	0
T77	780	0	0	0
T81	1136	0	0	0
T108	0	5	0	0
T227	0	3	0	0
T240	0	4387	0	0
T248	0	6	0	0
T249	0	1	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212434727	96241	0	0
T20	2928	0	0	0
T21	1506	0	0	0
T34	429449	4699	0	0
T35	202563	0	0	0
T36	0	2063	0	0
T46	2306	0	0	0
T60	2399	0	0	0
T73	6953	0	0	0
T91	1118	0	0	0
T92	1303	0	0	0
T100	1645	0	0	0
T240	0	5118	0	0
T241	0	11004	0	0
T242	0	4286	0	0
T243	0	3780	0	0
T244	0	2000	0	0
T245	0	6263	0	0
T246	0	1195	0	0
T247	0	1621	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212434727	93361	0	0
T5	34679	64	0	0
T10	4590	0	0	0
T11	1802	0	0	0
T12	3165	0	0	0
T16	2166	0	0	0
T22	1727	0	0	0
T30	1123	0	0	0
T34	0	4258	0	0
T36	0	2027	0	0
T37	1479	0	0	0
T43	3101	0	0	0
T47	0	6	0	0
T74	0	71	0	0
T75	3824	0	0	0
T108	0	7	0	0
T209	0	29	0	0
T240	0	4818	0	0
T241	0	9868	0	0
T248	0	7	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212434727	85261	0	0
T20	2928	0	0	0
T21	1506	0	0	0
T34	429449	4247	0	0
T35	202563	0	0	0
T36	0	1745	0	0
T46	2306	0	0	0
T60	2399	0	0	0
T73	6953	0	0	0
T91	1118	0	0	0
T92	1303	0	0	0
T100	1645	0	0	0
T240	0	4431	0	0
T241	0	9656	0	0
T242	0	3979	0	0
T243	0	3317	0	0
T244	0	1568	0	0
T245	0	5368	0	0
T246	0	996	0	0
T247	0	1400	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212434727	95079	0	0
T20	2928	0	0	0
T21	1506	0	0	0
T34	429449	4572	0	0
T35	202563	0	0	0
T36	0	1960	0	0
T46	2306	0	0	0
T60	2399	0	0	0
T73	6953	0	0	0
T91	1118	0	0	0
T92	1303	0	0	0
T100	1645	0	0	0
T240	0	5087	0	0
T241	0	10556	0	0
T242	0	4539	0	0
T243	0	3897	0	0
T244	0	2004	0	0
T245	0	5983	0	0
T246	0	1322	0	0
T247	0	1672	0	0