Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.29	98.25	93.91	97.02	92.44	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.21	99.92	92.66	82.54	92.44	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T10,T26

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T18,T19
1	0	Covered	T4,T29,T7

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T21,T10	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T1,T5,T35	Yes	T1,T5,T35	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T6	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T6,T21	Yes	T1,T6,T21	INPUT
edn_i[1].edn_req	Yes	Yes	T9,T10,T26	Yes	T9,T10,T26	INPUT
edn_i[2].edn_req	Yes	Yes	T2,T9,T22	Yes	T2,T9,T22	INPUT
edn_i[3].edn_req	Yes	Yes	T9,T36,T37	Yes	T9,T36,T37	INPUT
edn_i[4].edn_req	Yes	Yes	T10,T14,T26	Yes	T10,T14,T26	INPUT
edn_i[5].edn_req	Yes	Yes	T3,T36,T38	Yes	T3,T36,T38	INPUT
edn_i[6].edn_req	Yes	Yes	T39,T40,T11	Yes	T39,T40,T11	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T6,T21	Yes	T1,T6,T21	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T6,T21	Yes	T1,T6,T21	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T6,T21	Yes	T1,T6,T21	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T9,T10,T26	Yes	T9,T10,T26	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T9,T26,T38	Yes	T9,T26,T38	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T9,T10,T26	Yes	T9,T10,T26	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T2,T9,T22	Yes	T2,T9,T22	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T38,T39,T41	Yes	T2,T9,T22	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T2,T9,T22	Yes	T2,T9,T22	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T9,T36,T37	Yes	T9,T36,T37	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T20,T39,T8	Yes	T9,T36,T37	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T9,T36,T37	Yes	T9,T36,T37	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T10,T14,T26	Yes	T10,T14,T26	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T14,T37,T42	Yes	T14,T26,T37	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T10,T14,T26	Yes	T10,T14,T26	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T3,T36,T38	Yes	T3,T36,T38	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T37,T20,T43	Yes	T3,T37,T20	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T3,T36,T38	Yes	T3,T36,T38	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T39,T40,T44	Yes	T39,T40,T11	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T40,T44,T45	Yes	T40,T44,T46	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T39,T40,T11	Yes	T39,T40,T11	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T6,T21	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T6,T21	Yes	T1,T6,T21	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T6,T21	Yes	T1,T6,T21	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T10,T26,T47	Yes	T10,T26,T47	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T10,T26	Yes	T2,T10,T26	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T48,T29	Yes	T4,T48,T29	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T10,T26	Yes	T2,T10,T26	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T48,T29	Yes	T4,T48,T29	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T1,T5,T49	Yes	T1,T5,T49	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T5,T49	Yes	T1,T5,T49	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	230618338	230418300	0	0
CsrngAppIfOut_A	230618338	230418300	0	0
FpvSecCmCntAlertCheck_A	230618338	130	0	0
FpvSecCmGenCmdFifoRptrCheck_A	230618338	90	0	0
FpvSecCmGenCmdFifoWptrCheck_A	230618338	90	0	0
FpvSecCmMainFsmCheck_A	230618338	90	0	0
FpvSecCmRegWeOnehotCheck_A	230618338	90	0	0
FpvSecCmResCmdFifoRptrCheck_A	230618338	90	0	0
FpvSecCmResCmdFifoWptrCheck_A	230618338	90	0	0
IntrEdnCmdReqDoneKnownO_A	230618338	230418300	0	0
TlAReadyKnownO_A	230618338	230418300	0	0
TlDValidKnownO_A	230618338	230418300	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	230618338	90	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	230618338	90	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	230618338	90	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	230618338	90	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	230618338	90	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	230618338	90	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	230618338	90	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	230618338	576342	0	318
gen_edn_if_asserts[0].EdnDataStable_A	230618338	72822	0	441
gen_edn_if_asserts[0].EdnEndPointOut_A	230618338	230418300	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	230618338	160410	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	230618338	576342	0	318
gen_edn_if_asserts[1].EdnDataStable_A	230618338	4177	0	132
gen_edn_if_asserts[1].EdnEndPointOut_A	230618338	230418300	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	230618338	160410	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	230618338	576342	0	318
gen_edn_if_asserts[2].EdnDataStable_A	230618338	6792	0	132
gen_edn_if_asserts[2].EdnEndPointOut_A	230618338	230418300	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	230618338	160410	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	230618338	576342	0	318
gen_edn_if_asserts[3].EdnDataStable_A	230618338	3977	0	116
gen_edn_if_asserts[3].EdnEndPointOut_A	230618338	230418300	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	230618338	160410	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	230618338	576342	0	318
gen_edn_if_asserts[4].EdnDataStable_A	230618338	2548	0	102
gen_edn_if_asserts[4].EdnEndPointOut_A	230618338	230418300	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	230618338	160410	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	230618338	576342	0	318
gen_edn_if_asserts[5].EdnDataStable_A	230618338	1467	0	97
gen_edn_if_asserts[5].EdnEndPointOut_A	230618338	230418300	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	230618338	160410	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	230618338	576342	0	318
gen_edn_if_asserts[6].EdnDataStable_A	230618338	1571	0	77
gen_edn_if_asserts[6].EdnEndPointOut_A	230618338	230418300	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	230618338	160410	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	230418300	0	0
T1	164758	164750	0	0
T2	2233	2171	0	0
T3	964	882	0	0
T4	1140	1027	0	0
T6	3554	3484	0	0
T9	4135	4059	0	0
T10	2059	2004	0	0
T14	3608	3548	0	0
T21	2930	2861	0	0
T22	1718	1651	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	230418300	0	0
T1	164758	164750	0	0
T2	2233	2171	0	0
T3	964	882	0	0
T4	1140	1027	0	0
T6	3554	3484	0	0
T9	4135	4059	0	0
T10	2059	2004	0	0
T14	3608	3548	0	0
T21	2930	2861	0	0
T22	1718	1651	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	130	0	0
T15	763	1	0	0
T16	45182	20	0	0
T17	0	1	0	0
T18	0	20	0	0
T28	2014	0	0	0
T35	393690	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	1188	0	0	0
T57	467226	0	0	0
T58	19790	0	0	0
T59	925215	0	0	0
T60	3022	0	0	0
T61	1942	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	90	0	0
T16	45182	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T28	2014	0	0	0
T35	393690	0	0	0
T40	2963	0	0	0
T56	1188	0	0	0
T57	467226	0	0	0
T58	19790	0	0	0
T59	925215	0	0	0
T60	3022	0	0	0
T61	1942	0	0	0
T62	0	10	0	0
T63	0	20	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	90	0	0
T16	45182	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T28	2014	0	0	0
T35	393690	0	0	0
T40	2963	0	0	0
T56	1188	0	0	0
T57	467226	0	0	0
T58	19790	0	0	0
T59	925215	0	0	0
T60	3022	0	0	0
T61	1942	0	0	0
T62	0	10	0	0
T63	0	20	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	90	0	0
T16	45182	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T28	2014	0	0	0
T35	393690	0	0	0
T40	2963	0	0	0
T56	1188	0	0	0
T57	467226	0	0	0
T58	19790	0	0	0
T59	925215	0	0	0
T60	3022	0	0	0
T61	1942	0	0	0
T62	0	10	0	0
T63	0	20	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	90	0	0
T16	45182	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T28	2014	0	0	0
T35	393690	0	0	0
T40	2963	0	0	0
T56	1188	0	0	0
T57	467226	0	0	0
T58	19790	0	0	0
T59	925215	0	0	0
T60	3022	0	0	0
T61	1942	0	0	0
T62	0	10	0	0
T63	0	20	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	90	0	0
T16	45182	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T28	2014	0	0	0
T35	393690	0	0	0
T40	2963	0	0	0
T56	1188	0	0	0
T57	467226	0	0	0
T58	19790	0	0	0
T59	925215	0	0	0
T60	3022	0	0	0
T61	1942	0	0	0
T62	0	10	0	0
T63	0	20	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	90	0	0
T16	45182	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T28	2014	0	0	0
T35	393690	0	0	0
T40	2963	0	0	0
T56	1188	0	0	0
T57	467226	0	0	0
T58	19790	0	0	0
T59	925215	0	0	0
T60	3022	0	0	0
T61	1942	0	0	0
T62	0	10	0	0
T63	0	20	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	230418300	0	0
T1	164758	164750	0	0
T2	2233	2171	0	0
T3	964	882	0	0
T4	1140	1027	0	0
T6	3554	3484	0	0
T9	4135	4059	0	0
T10	2059	2004	0	0
T14	3608	3548	0	0
T21	2930	2861	0	0
T22	1718	1651	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	230418300	0	0
T1	164758	164750	0	0
T2	2233	2171	0	0
T3	964	882	0	0
T4	1140	1027	0	0
T6	3554	3484	0	0
T9	4135	4059	0	0
T10	2059	2004	0	0
T14	3608	3548	0	0
T21	2930	2861	0	0
T22	1718	1651	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	230418300	0	0
T1	164758	164750	0	0
T2	2233	2171	0	0
T3	964	882	0	0
T4	1140	1027	0	0
T6	3554	3484	0	0
T9	4135	4059	0	0
T10	2059	2004	0	0
T14	3608	3548	0	0
T21	2930	2861	0	0
T22	1718	1651	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	90	0	0
T16	45182	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T28	2014	0	0	0
T35	393690	0	0	0
T40	2963	0	0	0
T56	1188	0	0	0
T57	467226	0	0	0
T58	19790	0	0	0
T59	925215	0	0	0
T60	3022	0	0	0
T61	1942	0	0	0
T62	0	10	0	0
T63	0	20	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	90	0	0
T16	45182	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T28	2014	0	0	0
T35	393690	0	0	0
T40	2963	0	0	0
T56	1188	0	0	0
T57	467226	0	0	0
T58	19790	0	0	0
T59	925215	0	0	0
T60	3022	0	0	0
T61	1942	0	0	0
T62	0	10	0	0
T63	0	20	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	90	0	0
T16	45182	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T28	2014	0	0	0
T35	393690	0	0	0
T40	2963	0	0	0
T56	1188	0	0	0
T57	467226	0	0	0
T58	19790	0	0	0
T59	925215	0	0	0
T60	3022	0	0	0
T61	1942	0	0	0
T62	0	10	0	0
T63	0	20	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	90	0	0
T16	45182	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T28	2014	0	0	0
T35	393690	0	0	0
T40	2963	0	0	0
T56	1188	0	0	0
T57	467226	0	0	0
T58	19790	0	0	0
T59	925215	0	0	0
T60	3022	0	0	0
T61	1942	0	0	0
T62	0	10	0	0
T63	0	20	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	90	0	0
T16	45182	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T28	2014	0	0	0
T35	393690	0	0	0
T40	2963	0	0	0
T56	1188	0	0	0
T57	467226	0	0	0
T58	19790	0	0	0
T59	925215	0	0	0
T60	3022	0	0	0
T61	1942	0	0	0
T62	0	10	0	0
T63	0	20	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	90	0	0
T16	45182	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T28	2014	0	0	0
T35	393690	0	0	0
T40	2963	0	0	0
T56	1188	0	0	0
T57	467226	0	0	0
T58	19790	0	0	0
T59	925215	0	0	0
T60	3022	0	0	0
T61	1942	0	0	0
T62	0	10	0	0
T63	0	20	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	90	0	0
T16	45182	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T28	2014	0	0	0
T35	393690	0	0	0
T40	2963	0	0	0
T56	1188	0	0	0
T57	467226	0	0	0
T58	19790	0	0	0
T59	925215	0	0	0
T60	3022	0	0	0
T61	1942	0	0	0
T62	0	10	0	0
T63	0	20	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	576342	0	318
T1	164758	950	0	2
T2	2233	340	0	0
T3	964	21	0	0
T4	1140	808	0	0
T5	0	0	0	2
T6	3554	15	0	0
T9	4135	88	0	0
T10	2059	232	0	0
T14	3608	278	0	0
T21	2930	32	0	0
T22	1718	14	0	0
T48	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	72822	0	441
T1	164758	52	0	0
T2	2233	0	0	0
T3	964	0	0	0
T4	1140	0	0	0
T5	0	125	0	0
T6	3554	11	0	1
T9	4135	0	0	0
T10	2059	0	0	0
T14	3608	0	0	0
T21	2930	58	0	1
T22	1718	0	0	0
T37	0	0	0	1
T38	0	3	0	1
T47	0	4	0	1
T71	0	15	0	1
T72	0	3	0	1
T73	0	8	0	1
T74	0	4	0	1
T75	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	230418300	0	0
T1	164758	164750	0	0
T2	2233	2171	0	0
T3	964	882	0	0
T4	1140	1027	0	0
T6	3554	3484	0	0
T9	4135	4059	0	0
T10	2059	2004	0	0
T14	3608	3548	0	0
T21	2930	2861	0	0
T22	1718	1651	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	160410	0	0
T4	1140	217	0	0
T5	106977	0	0	0
T7	0	298	0	0
T15	0	404	0	0
T16	0	17567	0	0
T17	0	376	0	0
T26	2699	0	0	0
T27	0	7	0	0
T28	0	7	0	0
T29	0	646	0	0
T36	3166	0	0	0
T38	2079	0	0	0
T47	1832	0	0	0
T48	1079	0	0	0
T50	0	333	0	0
T61	0	1125	0	0
T71	2153	0	0	0
T72	1672	0	0	0
T73	1922	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	576342	0	318
T1	164758	950	0	2
T2	2233	340	0	0
T3	964	21	0	0
T4	1140	808	0	0
T5	0	0	0	2
T6	3554	15	0	0
T9	4135	88	0	0
T10	2059	232	0	0
T14	3608	278	0	0
T21	2930	32	0	0
T22	1718	14	0	0
T48	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	4177	0	132
T4	1140	0	0	0
T5	106977	0	0	0
T9	4135	519	0	1
T10	2059	4	0	1
T14	3608	0	0	0
T22	1718	0	0	0
T26	2699	4	0	0
T37	0	20	0	1
T38	0	12	0	1
T39	0	3	0	1
T40	0	0	0	1
T43	0	4	0	1
T47	1832	0	0	0
T48	1079	0	0	0
T71	2153	0	0	0
T76	0	3	0	1
T77	0	3	0	1
T78	0	36	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	230418300	0	0
T1	164758	164750	0	0
T2	2233	2171	0	0
T3	964	882	0	0
T4	1140	1027	0	0
T6	3554	3484	0	0
T9	4135	4059	0	0
T10	2059	2004	0	0
T14	3608	3548	0	0
T21	2930	2861	0	0
T22	1718	1651	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	160410	0	0
T4	1140	217	0	0
T5	106977	0	0	0
T7	0	298	0	0
T15	0	404	0	0
T16	0	17567	0	0
T17	0	376	0	0
T26	2699	0	0	0
T27	0	7	0	0
T28	0	7	0	0
T29	0	646	0	0
T36	3166	0	0	0
T38	2079	0	0	0
T47	1832	0	0	0
T48	1079	0	0	0
T50	0	333	0	0
T61	0	1125	0	0
T71	2153	0	0	0
T72	1672	0	0	0
T73	1922	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	576342	0	318
T1	164758	950	0	2
T2	2233	340	0	0
T3	964	21	0	0
T4	1140	808	0	0
T5	0	0	0	2
T6	3554	15	0	0
T9	4135	88	0	0
T10	2059	232	0	0
T14	3608	278	0	0
T21	2930	32	0	0
T22	1718	14	0	0
T48	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	6792	0	132
T2	2233	4	0	1
T3	964	0	0	0
T4	1140	1	0	0
T6	3554	0	0	0
T9	4135	3	0	1
T10	2059	0	0	0
T14	3608	0	0	0
T21	2930	0	0	0
T22	1718	3	0	1
T26	2699	0	0	0
T37	0	3	0	1
T38	0	30	0	1
T39	0	12	0	1
T40	0	0	0	1
T41	0	4	0	0
T79	0	3	0	1
T80	0	6	0	1
T81	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	230418300	0	0
T1	164758	164750	0	0
T2	2233	2171	0	0
T3	964	882	0	0
T4	1140	1027	0	0
T6	3554	3484	0	0
T9	4135	4059	0	0
T10	2059	2004	0	0
T14	3608	3548	0	0
T21	2930	2861	0	0
T22	1718	1651	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	160410	0	0
T4	1140	217	0	0
T5	106977	0	0	0
T7	0	298	0	0
T15	0	404	0	0
T16	0	17567	0	0
T17	0	376	0	0
T26	2699	0	0	0
T27	0	7	0	0
T28	0	7	0	0
T29	0	646	0	0
T36	3166	0	0	0
T38	2079	0	0	0
T47	1832	0	0	0
T48	1079	0	0	0
T50	0	333	0	0
T61	0	1125	0	0
T71	2153	0	0	0
T72	1672	0	0	0
T73	1922	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	576342	0	318
T1	164758	950	0	2
T2	2233	340	0	0
T3	964	21	0	0
T4	1140	808	0	0
T5	0	0	0	2
T6	3554	15	0	0
T9	4135	88	0	0
T10	2059	232	0	0
T14	3608	278	0	0
T21	2930	32	0	0
T22	1718	14	0	0
T48	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	3977	0	116
T4	1140	0	0	0
T5	106977	0	0	0
T9	4135	3	0	1
T10	2059	0	0	0
T14	3608	0	0	0
T20	0	23	0	1
T22	1718	0	0	0
T26	2699	0	0	0
T36	0	19	0	1
T37	0	11	0	1
T39	0	35	0	1
T40	0	3	0	1
T41	0	4	0	1
T47	1832	0	0	0
T48	1079	0	0	0
T60	0	4	0	0
T65	0	4	0	0
T71	2153	0	0	0
T81	0	0	0	1
T82	0	3	0	1
T83	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	230418300	0	0
T1	164758	164750	0	0
T2	2233	2171	0	0
T3	964	882	0	0
T4	1140	1027	0	0
T6	3554	3484	0	0
T9	4135	4059	0	0
T10	2059	2004	0	0
T14	3608	3548	0	0
T21	2930	2861	0	0
T22	1718	1651	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	160410	0	0
T4	1140	217	0	0
T5	106977	0	0	0
T7	0	298	0	0
T15	0	404	0	0
T16	0	17567	0	0
T17	0	376	0	0
T26	2699	0	0	0
T27	0	7	0	0
T28	0	7	0	0
T29	0	646	0	0
T36	3166	0	0	0
T38	2079	0	0	0
T47	1832	0	0	0
T48	1079	0	0	0
T50	0	333	0	0
T61	0	1125	0	0
T71	2153	0	0	0
T72	1672	0	0	0
T73	1922	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	576342	0	318
T1	164758	950	0	2
T2	2233	340	0	0
T3	964	21	0	0
T4	1140	808	0	0
T5	0	0	0	2
T6	3554	15	0	0
T9	4135	88	0	0
T10	2059	232	0	0
T14	3608	278	0	0
T21	2930	32	0	0
T22	1718	14	0	0
T48	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	2548	0	102
T4	1140	0	0	0
T5	106977	0	0	0
T10	2059	4	0	0
T14	3608	222	0	1
T26	2699	4	0	1
T37	0	8	0	1
T38	0	3	0	1
T39	0	3	0	1
T40	0	8	0	1
T42	0	30	0	1
T47	1832	0	0	0
T48	1079	0	0	0
T66	0	4	0	0
T67	0	4	0	0
T71	2153	0	0	0
T72	1672	0	0	0
T73	1922	0	0	0
T84	0	0	0	1
T85	0	0	0	1
T86	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	230418300	0	0
T1	164758	164750	0	0
T2	2233	2171	0	0
T3	964	882	0	0
T4	1140	1027	0	0
T6	3554	3484	0	0
T9	4135	4059	0	0
T10	2059	2004	0	0
T14	3608	3548	0	0
T21	2930	2861	0	0
T22	1718	1651	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	160410	0	0
T4	1140	217	0	0
T5	106977	0	0	0
T7	0	298	0	0
T15	0	404	0	0
T16	0	17567	0	0
T17	0	376	0	0
T26	2699	0	0	0
T27	0	7	0	0
T28	0	7	0	0
T29	0	646	0	0
T36	3166	0	0	0
T38	2079	0	0	0
T47	1832	0	0	0
T48	1079	0	0	0
T50	0	333	0	0
T61	0	1125	0	0
T71	2153	0	0	0
T72	1672	0	0	0
T73	1922	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	576342	0	318
T1	164758	950	0	2
T2	2233	340	0	0
T3	964	21	0	0
T4	1140	808	0	0
T5	0	0	0	2
T6	3554	15	0	0
T9	4135	88	0	0
T10	2059	232	0	0
T14	3608	278	0	0
T21	2930	32	0	0
T22	1718	14	0	0
T48	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	1467	0	97
T3	964	3	0	1
T4	1140	0	0	0
T6	3554	0	0	0
T9	4135	0	0	0
T10	2059	0	0	0
T14	3608	0	0	0
T20	0	39	0	1
T21	2930	0	0	0
T22	1718	0	0	0
T26	2699	0	0	0
T36	0	3	0	1
T37	0	57	0	1
T38	0	3	0	1
T39	0	3	0	1
T40	0	0	0	1
T43	0	4	0	0
T47	1832	0	0	0
T70	0	4	0	0
T80	0	7	0	1
T87	0	10	0	1
T88	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	230418300	0	0
T1	164758	164750	0	0
T2	2233	2171	0	0
T3	964	882	0	0
T4	1140	1027	0	0
T6	3554	3484	0	0
T9	4135	4059	0	0
T10	2059	2004	0	0
T14	3608	3548	0	0
T21	2930	2861	0	0
T22	1718	1651	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	160410	0	0
T4	1140	217	0	0
T5	106977	0	0	0
T7	0	298	0	0
T15	0	404	0	0
T16	0	17567	0	0
T17	0	376	0	0
T26	2699	0	0	0
T27	0	7	0	0
T28	0	7	0	0
T29	0	646	0	0
T36	3166	0	0	0
T38	2079	0	0	0
T47	1832	0	0	0
T48	1079	0	0	0
T50	0	333	0	0
T61	0	1125	0	0
T71	2153	0	0	0
T72	1672	0	0	0
T73	1922	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	576342	0	318
T1	164758	950	0	2
T2	2233	340	0	0
T3	964	21	0	0
T4	1140	808	0	0
T5	0	0	0	2
T6	3554	15	0	0
T9	4135	88	0	0
T10	2059	232	0	0
T14	3608	278	0	0
T21	2930	32	0	0
T22	1718	14	0	0
T48	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	1571	0	77
T7	1166	0	0	0
T11	0	3	0	1
T13	0	0	0	1
T27	1538	0	0	0
T39	1850	3	0	1
T40	0	57	0	1
T41	2964	0	0	0
T44	0	61	0	1
T45	0	55	0	1
T46	0	4	0	1
T65	2739	0	0	0
T77	1826	0	0	0
T82	728	0	0	0
T83	0	7	0	1
T87	2126	0	0	0
T89	0	4	0	0
T90	0	4	0	1
T91	0	4	0	0
T92	1213	0	0	0
T93	1309	0	0	0
T94	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	230418300	0	0
T1	164758	164750	0	0
T2	2233	2171	0	0
T3	964	882	0	0
T4	1140	1027	0	0
T6	3554	3484	0	0
T9	4135	4059	0	0
T10	2059	2004	0	0
T14	3608	3548	0	0
T21	2930	2861	0	0
T22	1718	1651	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230618338	160410	0	0
T4	1140	217	0	0
T5	106977	0	0	0
T7	0	298	0	0
T15	0	404	0	0
T16	0	17567	0	0
T17	0	376	0	0
T26	2699	0	0	0
T27	0	7	0	0
T28	0	7	0	0
T29	0	646	0	0
T36	3166	0	0	0
T38	2079	0	0	0
T47	1832	0	0	0
T48	1079	0	0	0
T50	0	333	0	0
T61	0	1125	0	0
T71	2153	0	0	0
T72	1672	0	0	0
T73	1922	0	0	0