Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	231159251	10317079	0	0
boot_gen_cmd_rd_A	231159251	47679	0	0
boot_ins_cmd_rd_A	231159251	54624	0	0
ctrl_rd_A	231159251	47069	0	0
err_code_test_rd_A	231159251	54439	0	0
intr_enable_rd_A	231159251	54209	0	0
max_num_reqs_between_reseeds_rd_A	231159251	47956	0	0
regwen_rd_A	231159251	55300	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231159251	10317079	0	0
T1	164758	91294	0	0
T2	2233	0	0	0
T3	964	0	0	0
T4	1140	0	0	0
T5	0	435771	0	0
T6	3554	0	0	0
T9	4135	0	0	0
T10	2059	0	0	0
T14	3608	0	0	0
T21	2930	0	0	0
T22	1718	0	0	0
T35	0	145865	0	0
T57	0	189987	0	0
T59	0	314910	0	0
T225	0	78080	0	0
T226	0	148534	0	0
T227	0	142830	0	0
T228	0	60026	0	0
T229	0	168829	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231159251	47679	0	0
T23	970	0	0	0
T28	2014	0	0	0
T35	393690	2318	0	0
T40	2963	0	0	0
T56	1188	0	0	0
T57	467226	0	0	0
T58	19790	0	0	0
T59	925215	8775	0	0
T60	3022	0	0	0
T61	1942	0	0	0
T226	0	4194	0	0
T227	0	4031	0	0
T230	0	1207	0	0
T231	0	1307	0	0
T232	0	3291	0	0
T233	0	5507	0	0
T234	0	3600	0	0
T235	0	3673	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231159251	54624	0	0
T23	970	0	0	0
T28	2014	0	0	0
T35	393690	2609	0	0
T40	2963	0	0	0
T56	1188	0	0	0
T57	467226	0	0	0
T58	19790	0	0	0
T59	925215	10059	0	0
T60	3022	0	0	0
T61	1942	0	0	0
T226	0	4956	0	0
T227	0	4527	0	0
T230	0	1583	0	0
T231	0	1456	0	0
T232	0	3561	0	0
T233	0	6637	0	0
T234	0	4122	0	0
T235	0	3717	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231159251	47069	0	0
T35	0	2190	0	0
T43	1941	0	0	0
T52	0	6	0	0
T59	0	8666	0	0
T60	0	4	0	0
T61	0	3	0	0
T67	2199	7	0	0
T68	1168	0	0	0
T69	8344	0	0	0
T70	2623	0	0	0
T78	3695	0	0	0
T103	2393	0	0	0
T226	0	4558	0	0
T227	0	4117	0	0
T236	0	5	0	0
T237	0	2	0	0
T238	1798	0	0	0
T239	1157	0	0	0
T240	2113	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231159251	54439	0	0
T23	970	0	0	0
T28	2014	0	0	0
T35	393690	2730	0	0
T40	2963	0	0	0
T56	1188	0	0	0
T57	467226	0	0	0
T58	19790	0	0	0
T59	925215	9981	0	0
T60	3022	0	0	0
T61	1942	0	0	0
T226	0	4733	0	0
T227	0	4516	0	0
T230	0	1532	0	0
T231	0	1545	0	0
T232	0	3998	0	0
T233	0	6159	0	0
T234	0	4235	0	0
T235	0	4028	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231159251	54209	0	0
T23	970	0	0	0
T28	2014	0	0	0
T35	393690	2461	0	0
T40	2963	0	0	0
T56	1188	0	0	0
T57	467226	0	0	0
T58	19790	0	0	0
T59	925215	9386	0	0
T60	3022	0	0	0
T61	1942	0	0	0
T201	0	37	0	0
T226	0	4809	0	0
T227	0	4471	0	0
T230	0	1505	0	0
T231	0	1601	0	0
T237	0	18	0	0
T241	0	98	0	0
T242	0	29	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231159251	47956	0	0
T23	970	0	0	0
T28	2014	0	0	0
T35	393690	2087	0	0
T40	2963	0	0	0
T56	1188	0	0	0
T57	467226	0	0	0
T58	19790	0	0	0
T59	925215	9154	0	0
T60	3022	0	0	0
T61	1942	0	0	0
T226	0	4252	0	0
T227	0	3970	0	0
T230	0	1310	0	0
T231	0	1303	0	0
T232	0	2968	0	0
T233	0	5405	0	0
T234	0	3593	0	0
T235	0	3300	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231159251	55300	0	0
T23	970	0	0	0
T28	2014	0	0	0
T35	393690	2786	0	0
T40	2963	0	0	0
T56	1188	0	0	0
T57	467226	0	0	0
T58	19790	0	0	0
T59	925215	9798	0	0
T60	3022	0	0	0
T61	1942	0	0	0
T226	0	4799	0	0
T227	0	4801	0	0
T230	0	1661	0	0
T231	0	1636	0	0
T232	0	3721	0	0
T233	0	6198	0	0
T234	0	3934	0	0
T235	0	3969	0	0