Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 94.44 83.33 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.09 98.25 93.91 96.97 91.28 96.37 99.77


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
edn_csr_assert 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_edn_core 93.97 99.92 92.66 82.25 91.28 98.83 98.88
u_edn_cov_if 25.00 50.00 0.00
u_reg 96.95 95.02 97.57 100.00 92.16 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Cond Coverage for Module : edn
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT3,T20,T29

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT16,T17,T18
10CoveredT1,T29,T34

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 69 69 100.00
Total Bits 1172 1172 100.00
Total Bits 0->1 586 586 100.00
Total Bits 1->0 586 586 100.00

Ports 69 69 100.00
Port Bits 1172 1172 100.00
Port Bits 0->1 586 586 100.00
Port Bits 1->0 586 586 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T2,T3,T20 Yes T2,T3,T20 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T2,T3,T20 Yes T2,T3,T20 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T2,T4,T38 Yes T2,T4,T38 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T2,T3,T20 Yes T2,T3,T20 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T2,T3,T21 Yes T2,T3,T21 INPUT
edn_i[1].edn_req Yes Yes T8,T9,T39 Yes T8,T9,T39 INPUT
edn_i[2].edn_req Yes Yes T8,T9,T40 Yes T8,T9,T40 INPUT
edn_i[3].edn_req Yes Yes T1,T8,T40 Yes T1,T8,T40 INPUT
edn_i[4].edn_req Yes Yes T40,T39,T41 Yes T40,T39,T41 INPUT
edn_i[5].edn_req Yes Yes T9,T15,T29 Yes T9,T15,T29 INPUT
edn_i[6].edn_req Yes Yes T20,T9,T39 Yes T20,T9,T39 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T2,T3,T21 Yes T2,T3,T21 OUTPUT
edn_o[0].edn_fips Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
edn_o[0].edn_ack Yes Yes T2,T3,T21 Yes T2,T3,T21 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T8,T9,T41 Yes T8,T9,T39 OUTPUT
edn_o[1].edn_fips Yes Yes T8,T41,T42 Yes T8,T9,T39 OUTPUT
edn_o[1].edn_ack Yes Yes T8,T9,T39 Yes T8,T9,T39 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T8,T9,T40 Yes T8,T9,T40 OUTPUT
edn_o[2].edn_fips Yes Yes T8,T40,T41 Yes T8,T40,T41 OUTPUT
edn_o[2].edn_ack Yes Yes T8,T9,T40 Yes T8,T9,T40 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T1,T8,T40 Yes T1,T8,T40 OUTPUT
edn_o[3].edn_fips Yes Yes T8,T43,T10 Yes T8,T27,T43 OUTPUT
edn_o[3].edn_ack Yes Yes T1,T8,T40 Yes T1,T8,T40 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T40,T41,T10 Yes T40,T41,T10 OUTPUT
edn_o[4].edn_fips Yes Yes T40,T41,T44 Yes T40,T39,T41 OUTPUT
edn_o[4].edn_ack Yes Yes T40,T39,T41 Yes T40,T39,T41 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T9,T15,T39 Yes T9,T15,T45 OUTPUT
edn_o[5].edn_fips Yes Yes T9,T39,T44 Yes T9,T15,T45 OUTPUT
edn_o[5].edn_ack Yes Yes T9,T15,T45 Yes T9,T15,T45 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T20,T9,T39 Yes T20,T9,T39 OUTPUT
edn_o[6].edn_fips Yes Yes T9,T39,T42 Yes T9,T39,T10 OUTPUT
edn_o[6].edn_ack Yes Yes T20,T9,T39 Yes T20,T9,T39 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T2,T3,T4 Yes T2,T4,T8 INPUT
csrng_cmd_i.genbits_fips Yes Yes T2,T4,T8 Yes T2,T4,T8 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] Yes Yes T29,T28,T46 Yes T29,T28,T46 INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T3,T20,T29 Yes T3,T20,T29 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T1,T29,T47 Yes T1,T29,T47 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T3,T20,T29 Yes T3,T20,T29 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T1,T29,T47 Yes T1,T29,T47 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T2,T4,T48 Yes T2,T4,T48 OUTPUT
intr_edn_fatal_err_o Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : edn
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 47 47 100.00 47 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 47 47 100.00 47 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertTxKnownO_A 208936469 208777063 0 0
CsrngAppIfOut_A 208936469 208777063 0 0
FpvSecCmCntAlertCheck_A 208936469 83 0 0
FpvSecCmGenCmdFifoRptrCheck_A 208936469 50 0 0
FpvSecCmGenCmdFifoWptrCheck_A 208936469 50 0 0
FpvSecCmMainFsmCheck_A 208936469 50 0 0
FpvSecCmRegWeOnehotCheck_A 208936469 50 0 0
FpvSecCmResCmdFifoRptrCheck_A 208936469 50 0 0
FpvSecCmResCmdFifoWptrCheck_A 208936469 50 0 0
IntrEdnCmdReqDoneKnownO_A 208936469 208777063 0 0
TlAReadyKnownO_A 208936469 208777063 0 0
TlDValidKnownO_A 208936469 208777063 0 0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A 208936469 50 0 0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A 208936469 50 0 0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A 208936469 50 0 0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A 208936469 50 0 0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A 208936469 50 0 0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A 208936469 50 0 0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A 208936469 50 0 0
gen_edn_if_asserts[0].EdnDataStableDisable_A 208936469 564404 0 314
gen_edn_if_asserts[0].EdnDataStable_A 208936469 72297 0 435
gen_edn_if_asserts[0].EdnEndPointOut_A 208936469 208777063 0 0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A 208936469 127880 0 0
gen_edn_if_asserts[1].EdnDataStableDisable_A 208936469 564404 0 314
gen_edn_if_asserts[1].EdnDataStable_A 208936469 6284 0 152
gen_edn_if_asserts[1].EdnEndPointOut_A 208936469 208777063 0 0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A 208936469 127880 0 0
gen_edn_if_asserts[2].EdnDataStableDisable_A 208936469 564404 0 314
gen_edn_if_asserts[2].EdnDataStable_A 208936469 3875 0 131
gen_edn_if_asserts[2].EdnEndPointOut_A 208936469 208777063 0 0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A 208936469 127880 0 0
gen_edn_if_asserts[3].EdnDataStableDisable_A 208936469 564404 0 314
gen_edn_if_asserts[3].EdnDataStable_A 208936469 7604 0 117
gen_edn_if_asserts[3].EdnEndPointOut_A 208936469 208777063 0 0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A 208936469 127880 0 0
gen_edn_if_asserts[4].EdnDataStableDisable_A 208936469 564404 0 314
gen_edn_if_asserts[4].EdnDataStable_A 208936469 5448 0 111
gen_edn_if_asserts[4].EdnEndPointOut_A 208936469 208777063 0 0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A 208936469 127880 0 0
gen_edn_if_asserts[5].EdnDataStableDisable_A 208936469 564404 0 314
gen_edn_if_asserts[5].EdnDataStable_A 208936469 4465 0 98
gen_edn_if_asserts[5].EdnEndPointOut_A 208936469 208777063 0 0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A 208936469 127880 0 0
gen_edn_if_asserts[6].EdnDataStableDisable_A 208936469 564404 0 314
gen_edn_if_asserts[6].EdnDataStable_A 208936469 2377 0 86
gen_edn_if_asserts[6].EdnEndPointOut_A 208936469 208777063 0 0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A 208936469 127880 0 0


AlertTxKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 208777063 0 0
T1 1033 891 0 0
T2 188174 188162 0 0
T3 3050 2997 0 0
T4 945335 945325 0 0
T8 5418 5339 0 0
T9 3130 3046 0 0
T20 2209 2154 0 0
T21 1655 1571 0 0
T22 1332 1245 0 0
T23 1915 1832 0 0

CsrngAppIfOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 208777063 0 0
T1 1033 891 0 0
T2 188174 188162 0 0
T3 3050 2997 0 0
T4 945335 945325 0 0
T8 5418 5339 0 0
T9 3130 3046 0 0
T20 2209 2154 0 0
T21 1655 1571 0 0
T22 1332 1245 0 0
T23 1915 1832 0 0

FpvSecCmCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 83 0 0
T1 1033 1 0 0
T2 188174 0 0 0
T3 3050 0 0 0
T4 945335 0 0 0
T8 5418 0 0 0
T9 3130 0 0 0
T13 0 1 0 0
T14 0 1 0 0
T16 0 10 0 0
T20 2209 0 0 0
T21 1655 0 0 0
T22 1332 0 0 0
T23 1915 0 0 0
T49 0 1 0 0
T50 0 1 0 0
T51 0 1 0 0
T52 0 1 0 0
T53 0 1 0 0
T54 0 1 0 0

FpvSecCmGenCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 50 0 0
T16 27263 10 0 0
T17 0 10 0 0
T18 0 10 0 0
T55 0 10 0 0
T56 0 10 0 0
T57 1263 0 0 0
T58 1825 0 0 0
T59 3075 0 0 0
T60 1757 0 0 0
T61 1747 0 0 0
T62 16802 0 0 0
T63 1042 0 0 0
T64 2157 0 0 0
T65 2174 0 0 0

FpvSecCmGenCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 50 0 0
T16 27263 10 0 0
T17 0 10 0 0
T18 0 10 0 0
T55 0 10 0 0
T56 0 10 0 0
T57 1263 0 0 0
T58 1825 0 0 0
T59 3075 0 0 0
T60 1757 0 0 0
T61 1747 0 0 0
T62 16802 0 0 0
T63 1042 0 0 0
T64 2157 0 0 0
T65 2174 0 0 0

FpvSecCmMainFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 50 0 0
T16 27263 10 0 0
T17 0 10 0 0
T18 0 10 0 0
T55 0 10 0 0
T56 0 10 0 0
T57 1263 0 0 0
T58 1825 0 0 0
T59 3075 0 0 0
T60 1757 0 0 0
T61 1747 0 0 0
T62 16802 0 0 0
T63 1042 0 0 0
T64 2157 0 0 0
T65 2174 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 50 0 0
T16 27263 10 0 0
T17 0 10 0 0
T18 0 10 0 0
T55 0 10 0 0
T56 0 10 0 0
T57 1263 0 0 0
T58 1825 0 0 0
T59 3075 0 0 0
T60 1757 0 0 0
T61 1747 0 0 0
T62 16802 0 0 0
T63 1042 0 0 0
T64 2157 0 0 0
T65 2174 0 0 0

FpvSecCmResCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 50 0 0
T16 27263 10 0 0
T17 0 10 0 0
T18 0 10 0 0
T55 0 10 0 0
T56 0 10 0 0
T57 1263 0 0 0
T58 1825 0 0 0
T59 3075 0 0 0
T60 1757 0 0 0
T61 1747 0 0 0
T62 16802 0 0 0
T63 1042 0 0 0
T64 2157 0 0 0
T65 2174 0 0 0

FpvSecCmResCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 50 0 0
T16 27263 10 0 0
T17 0 10 0 0
T18 0 10 0 0
T55 0 10 0 0
T56 0 10 0 0
T57 1263 0 0 0
T58 1825 0 0 0
T59 3075 0 0 0
T60 1757 0 0 0
T61 1747 0 0 0
T62 16802 0 0 0
T63 1042 0 0 0
T64 2157 0 0 0
T65 2174 0 0 0

IntrEdnCmdReqDoneKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 208777063 0 0
T1 1033 891 0 0
T2 188174 188162 0 0
T3 3050 2997 0 0
T4 945335 945325 0 0
T8 5418 5339 0 0
T9 3130 3046 0 0
T20 2209 2154 0 0
T21 1655 1571 0 0
T22 1332 1245 0 0
T23 1915 1832 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 208777063 0 0
T1 1033 891 0 0
T2 188174 188162 0 0
T3 3050 2997 0 0
T4 945335 945325 0 0
T8 5418 5339 0 0
T9 3130 3046 0 0
T20 2209 2154 0 0
T21 1655 1571 0 0
T22 1332 1245 0 0
T23 1915 1832 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 208777063 0 0
T1 1033 891 0 0
T2 188174 188162 0 0
T3 3050 2997 0 0
T4 945335 945325 0 0
T8 5418 5339 0 0
T9 3130 3046 0 0
T20 2209 2154 0 0
T21 1655 1571 0 0
T22 1332 1245 0 0
T23 1915 1832 0 0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 50 0 0
T16 27263 10 0 0
T17 0 10 0 0
T18 0 10 0 0
T55 0 10 0 0
T56 0 10 0 0
T57 1263 0 0 0
T58 1825 0 0 0
T59 3075 0 0 0
T60 1757 0 0 0
T61 1747 0 0 0
T62 16802 0 0 0
T63 1042 0 0 0
T64 2157 0 0 0
T65 2174 0 0 0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 50 0 0
T16 27263 10 0 0
T17 0 10 0 0
T18 0 10 0 0
T55 0 10 0 0
T56 0 10 0 0
T57 1263 0 0 0
T58 1825 0 0 0
T59 3075 0 0 0
T60 1757 0 0 0
T61 1747 0 0 0
T62 16802 0 0 0
T63 1042 0 0 0
T64 2157 0 0 0
T65 2174 0 0 0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 50 0 0
T16 27263 10 0 0
T17 0 10 0 0
T18 0 10 0 0
T55 0 10 0 0
T56 0 10 0 0
T57 1263 0 0 0
T58 1825 0 0 0
T59 3075 0 0 0
T60 1757 0 0 0
T61 1747 0 0 0
T62 16802 0 0 0
T63 1042 0 0 0
T64 2157 0 0 0
T65 2174 0 0 0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 50 0 0
T16 27263 10 0 0
T17 0 10 0 0
T18 0 10 0 0
T55 0 10 0 0
T56 0 10 0 0
T57 1263 0 0 0
T58 1825 0 0 0
T59 3075 0 0 0
T60 1757 0 0 0
T61 1747 0 0 0
T62 16802 0 0 0
T63 1042 0 0 0
T64 2157 0 0 0
T65 2174 0 0 0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 50 0 0
T16 27263 10 0 0
T17 0 10 0 0
T18 0 10 0 0
T55 0 10 0 0
T56 0 10 0 0
T57 1263 0 0 0
T58 1825 0 0 0
T59 3075 0 0 0
T60 1757 0 0 0
T61 1747 0 0 0
T62 16802 0 0 0
T63 1042 0 0 0
T64 2157 0 0 0
T65 2174 0 0 0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 50 0 0
T16 27263 10 0 0
T17 0 10 0 0
T18 0 10 0 0
T55 0 10 0 0
T56 0 10 0 0
T57 1263 0 0 0
T58 1825 0 0 0
T59 3075 0 0 0
T60 1757 0 0 0
T61 1747 0 0 0
T62 16802 0 0 0
T63 1042 0 0 0
T64 2157 0 0 0
T65 2174 0 0 0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 50 0 0
T16 27263 10 0 0
T17 0 10 0 0
T18 0 10 0 0
T55 0 10 0 0
T56 0 10 0 0
T57 1263 0 0 0
T58 1825 0 0 0
T59 3075 0 0 0
T60 1757 0 0 0
T61 1747 0 0 0
T62 16802 0 0 0
T63 1042 0 0 0
T64 2157 0 0 0
T65 2174 0 0 0

gen_edn_if_asserts[0].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 564404 0 314
T1 1033 347 0 0
T2 188174 1254 0 2
T3 3050 332 0 0
T4 945335 2140 0 2
T8 5418 196 0 0
T9 3130 181 0 0
T15 0 0 0 2
T20 2209 131 0 0
T21 1655 33 0 0
T22 1332 14 0 0
T23 1915 18 0 0
T38 0 0 0 2
T47 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2

gen_edn_if_asserts[0].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 72297 0 435
T2 188174 161 0 0
T3 3050 8 0 1
T4 945335 123 0 0
T8 5418 611 0 1
T9 3130 279 0 1
T20 2209 0 0 0
T21 1655 3 0 1
T22 1332 3 0 1
T23 1915 3 0 1
T24 0 0 0 1
T26 940 4 0 0
T40 0 61 0 1
T43 0 0 0 1
T48 0 0 0 1

gen_edn_if_asserts[0].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 208777063 0 0
T1 1033 891 0 0
T2 188174 188162 0 0
T3 3050 2997 0 0
T4 945335 945325 0 0
T8 5418 5339 0 0
T9 3130 3046 0 0
T20 2209 2154 0 0
T21 1655 1571 0 0
T22 1332 1245 0 0
T23 1915 1832 0 0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 127880 0 0
T1 1033 419 0 0
T2 188174 0 0 0
T3 3050 0 0 0
T4 945335 0 0 0
T5 0 401 0 0
T6 0 612 0 0
T7 0 272 0 0
T8 5418 0 0 0
T9 3130 0 0 0
T20 2209 0 0 0
T21 1655 0 0 0
T22 1332 0 0 0
T23 1915 0 0 0
T29 0 417 0 0
T34 0 1112 0 0
T46 0 1012 0 0
T71 0 377 0 0
T72 0 917 0 0
T73 0 352 0 0

gen_edn_if_asserts[1].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 564404 0 314
T1 1033 347 0 0
T2 188174 1254 0 2
T3 3050 332 0 0
T4 945335 2140 0 2
T8 5418 196 0 0
T9 3130 181 0 0
T15 0 0 0 2
T20 2209 131 0 0
T21 1655 33 0 0
T22 1332 14 0 0
T23 1915 18 0 0
T38 0 0 0 2
T47 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2

gen_edn_if_asserts[1].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 6284 0 152
T8 5418 48 0 1
T9 3130 3 0 1
T10 0 3 0 1
T15 2364 0 0 0
T23 1915 0 0 0
T24 1536 0 0 0
T26 940 0 0 0
T29 855 0 0 0
T39 0 3 0 1
T40 1999 0 0 0
T41 0 11 0 1
T44 0 3 0 1
T47 1314 0 0 0
T48 22423 0 0 0
T74 0 3 0 1
T75 0 4 0 1
T76 0 3 0 1
T77 0 4 0 1

gen_edn_if_asserts[1].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 208777063 0 0
T1 1033 891 0 0
T2 188174 188162 0 0
T3 3050 2997 0 0
T4 945335 945325 0 0
T8 5418 5339 0 0
T9 3130 3046 0 0
T20 2209 2154 0 0
T21 1655 1571 0 0
T22 1332 1245 0 0
T23 1915 1832 0 0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 127880 0 0
T1 1033 419 0 0
T2 188174 0 0 0
T3 3050 0 0 0
T4 945335 0 0 0
T5 0 401 0 0
T6 0 612 0 0
T7 0 272 0 0
T8 5418 0 0 0
T9 3130 0 0 0
T20 2209 0 0 0
T21 1655 0 0 0
T22 1332 0 0 0
T23 1915 0 0 0
T29 0 417 0 0
T34 0 1112 0 0
T46 0 1012 0 0
T71 0 377 0 0
T72 0 917 0 0
T73 0 352 0 0

gen_edn_if_asserts[2].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 564404 0 314
T1 1033 347 0 0
T2 188174 1254 0 2
T3 3050 332 0 0
T4 945335 2140 0 2
T8 5418 196 0 0
T9 3130 181 0 0
T15 0 0 0 2
T20 2209 131 0 0
T21 1655 33 0 0
T22 1332 14 0 0
T23 1915 18 0 0
T38 0 0 0 2
T47 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2

gen_edn_if_asserts[2].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 3875 0 131
T8 5418 56 0 1
T9 3130 3 0 1
T15 2364 0 0 0
T23 1915 0 0 0
T24 1536 0 0 0
T26 940 0 0 0
T29 855 0 0 0
T39 0 3 0 1
T40 1999 14 0 1
T41 0 12 0 1
T44 0 3 0 1
T47 1314 0 0 0
T48 22423 0 0 0
T76 0 43 0 1
T78 0 4 0 1
T79 0 8 0 1
T80 0 58 0 1

gen_edn_if_asserts[2].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 208777063 0 0
T1 1033 891 0 0
T2 188174 188162 0 0
T3 3050 2997 0 0
T4 945335 945325 0 0
T8 5418 5339 0 0
T9 3130 3046 0 0
T20 2209 2154 0 0
T21 1655 1571 0 0
T22 1332 1245 0 0
T23 1915 1832 0 0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 127880 0 0
T1 1033 419 0 0
T2 188174 0 0 0
T3 3050 0 0 0
T4 945335 0 0 0
T5 0 401 0 0
T6 0 612 0 0
T7 0 272 0 0
T8 5418 0 0 0
T9 3130 0 0 0
T20 2209 0 0 0
T21 1655 0 0 0
T22 1332 0 0 0
T23 1915 0 0 0
T29 0 417 0 0
T34 0 1112 0 0
T46 0 1012 0 0
T71 0 377 0 0
T72 0 917 0 0
T73 0 352 0 0

gen_edn_if_asserts[3].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 564404 0 314
T1 1033 347 0 0
T2 188174 1254 0 2
T3 3050 332 0 0
T4 945335 2140 0 2
T8 5418 196 0 0
T9 3130 181 0 0
T15 0 0 0 2
T20 2209 131 0 0
T21 1655 33 0 0
T22 1332 14 0 0
T23 1915 18 0 0
T38 0 0 0 2
T47 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2

gen_edn_if_asserts[3].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 7604 0 117
T1 1033 1 0 0
T2 188174 0 0 0
T3 3050 0 0 0
T4 945335 0 0 0
T8 5418 42 0 1
T9 3130 0 0 0
T10 0 26 0 1
T20 2209 0 0 0
T21 1655 0 0 0
T22 1332 0 0 0
T23 1915 0 0 0
T27 0 19 0 1
T39 0 13 0 1
T40 0 12 0 1
T43 0 28 0 1
T44 0 0 0 1
T80 0 75 0 1
T81 0 3 0 1
T82 0 4 0 1

gen_edn_if_asserts[3].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 208777063 0 0
T1 1033 891 0 0
T2 188174 188162 0 0
T3 3050 2997 0 0
T4 945335 945325 0 0
T8 5418 5339 0 0
T9 3130 3046 0 0
T20 2209 2154 0 0
T21 1655 1571 0 0
T22 1332 1245 0 0
T23 1915 1832 0 0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 127880 0 0
T1 1033 419 0 0
T2 188174 0 0 0
T3 3050 0 0 0
T4 945335 0 0 0
T5 0 401 0 0
T6 0 612 0 0
T7 0 272 0 0
T8 5418 0 0 0
T9 3130 0 0 0
T20 2209 0 0 0
T21 1655 0 0 0
T22 1332 0 0 0
T23 1915 0 0 0
T29 0 417 0 0
T34 0 1112 0 0
T46 0 1012 0 0
T71 0 377 0 0
T72 0 917 0 0
T73 0 352 0 0

gen_edn_if_asserts[4].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 564404 0 314
T1 1033 347 0 0
T2 188174 1254 0 2
T3 3050 332 0 0
T4 945335 2140 0 2
T8 5418 196 0 0
T9 3130 181 0 0
T15 0 0 0 2
T20 2209 131 0 0
T21 1655 33 0 0
T22 1332 14 0 0
T23 1915 18 0 0
T38 0 0 0 2
T47 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2

gen_edn_if_asserts[4].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 5448 0 111
T10 0 3 0 1
T11 0 3 0 1
T15 2364 0 0 0
T24 1536 0 0 0
T25 1005 0 0 0
T27 2760 0 0 0
T28 2203 0 0 0
T29 855 0 0 0
T39 0 3 0 1
T40 1999 54 0 1
T41 0 59 0 1
T42 0 15 0 1
T43 1217 0 0 0
T44 0 15 0 1
T47 1314 0 0 0
T48 22423 0 0 0
T69 0 4 0 0
T83 0 47 0 1
T84 0 38 0 1
T85 0 0 0 1

gen_edn_if_asserts[4].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 208777063 0 0
T1 1033 891 0 0
T2 188174 188162 0 0
T3 3050 2997 0 0
T4 945335 945325 0 0
T8 5418 5339 0 0
T9 3130 3046 0 0
T20 2209 2154 0 0
T21 1655 1571 0 0
T22 1332 1245 0 0
T23 1915 1832 0 0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 127880 0 0
T1 1033 419 0 0
T2 188174 0 0 0
T3 3050 0 0 0
T4 945335 0 0 0
T5 0 401 0 0
T6 0 612 0 0
T7 0 272 0 0
T8 5418 0 0 0
T9 3130 0 0 0
T20 2209 0 0 0
T21 1655 0 0 0
T22 1332 0 0 0
T23 1915 0 0 0
T29 0 417 0 0
T34 0 1112 0 0
T46 0 1012 0 0
T71 0 377 0 0
T72 0 917 0 0
T73 0 352 0 0

gen_edn_if_asserts[5].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 564404 0 314
T1 1033 347 0 0
T2 188174 1254 0 2
T3 3050 332 0 0
T4 945335 2140 0 2
T8 5418 196 0 0
T9 3130 181 0 0
T15 0 0 0 2
T20 2209 131 0 0
T21 1655 33 0 0
T22 1332 14 0 0
T23 1915 18 0 0
T38 0 0 0 2
T47 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2

gen_edn_if_asserts[5].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 4465 0 98
T9 3130 16 0 1
T10 0 3 0 1
T11 0 3 0 1
T15 2364 4 0 0
T23 1915 0 0 0
T24 1536 0 0 0
T26 940 0 0 0
T27 2760 0 0 0
T29 855 0 0 0
T39 0 40 0 1
T40 1999 0 0 0
T44 0 24 0 1
T45 0 4 0 1
T47 1314 0 0 0
T48 22423 0 0 0
T83 0 3 0 1
T84 0 7 0 1
T86 0 3 0 1
T87 0 0 0 1

gen_edn_if_asserts[5].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 208777063 0 0
T1 1033 891 0 0
T2 188174 188162 0 0
T3 3050 2997 0 0
T4 945335 945325 0 0
T8 5418 5339 0 0
T9 3130 3046 0 0
T20 2209 2154 0 0
T21 1655 1571 0 0
T22 1332 1245 0 0
T23 1915 1832 0 0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 127880 0 0
T1 1033 419 0 0
T2 188174 0 0 0
T3 3050 0 0 0
T4 945335 0 0 0
T5 0 401 0 0
T6 0 612 0 0
T7 0 272 0 0
T8 5418 0 0 0
T9 3130 0 0 0
T20 2209 0 0 0
T21 1655 0 0 0
T22 1332 0 0 0
T23 1915 0 0 0
T29 0 417 0 0
T34 0 1112 0 0
T46 0 1012 0 0
T71 0 377 0 0
T72 0 917 0 0
T73 0 352 0 0

gen_edn_if_asserts[6].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 564404 0 314
T1 1033 347 0 0
T2 188174 1254 0 2
T3 3050 332 0 0
T4 945335 2140 0 2
T8 5418 196 0 0
T9 3130 181 0 0
T15 0 0 0 2
T20 2209 131 0 0
T21 1655 33 0 0
T22 1332 14 0 0
T23 1915 18 0 0
T38 0 0 0 2
T47 0 0 0 2
T66 0 0 0 2
T67 0 0 0 2
T68 0 0 0 2
T69 0 0 0 2
T70 0 0 0 2

gen_edn_if_asserts[6].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 2377 0 86
T4 945335 0 0 0
T8 5418 0 0 0
T9 3130 29 0 1
T10 0 3 0 1
T11 0 15 0 1
T15 2364 0 0 0
T20 2209 4 0 1
T21 1655 0 0 0
T22 1332 0 0 0
T23 1915 0 0 0
T26 940 0 0 0
T39 0 60 0 1
T40 1999 0 0 0
T42 0 39 0 1
T83 0 3 0 1
T84 0 3 0 1
T88 0 3 0 1
T89 0 17 0 1

gen_edn_if_asserts[6].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 208777063 0 0
T1 1033 891 0 0
T2 188174 188162 0 0
T3 3050 2997 0 0
T4 945335 945325 0 0
T8 5418 5339 0 0
T9 3130 3046 0 0
T20 2209 2154 0 0
T21 1655 1571 0 0
T22 1332 1245 0 0
T23 1915 1832 0 0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936469 127880 0 0
T1 1033 419 0 0
T2 188174 0 0 0
T3 3050 0 0 0
T4 945335 0 0 0
T5 0 401 0 0
T6 0 612 0 0
T7 0 272 0 0
T8 5418 0 0 0
T9 3130 0 0 0
T20 2209 0 0 0
T21 1655 0 0 0
T22 1332 0 0 0
T23 1915 0 0 0
T29 0 417 0 0
T34 0 1112 0 0
T46 0 1012 0 0
T71 0 377 0 0
T72 0 917 0 0
T73 0 352 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%