Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	209425837	9766882	0	0
boot_gen_cmd_rd_A	209425837	43020	0	0
boot_ins_cmd_rd_A	209425837	49678	0	0
ctrl_rd_A	209425837	42840	0	0
err_code_test_rd_A	209425837	50323	0	0
intr_enable_rd_A	209425837	50236	0	0
max_num_reqs_between_reseeds_rd_A	209425837	43935	0	0
regwen_rd_A	209425837	50580	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209425837	9766882	0	0
T2	188174	99328	0	0
T3	3050	0	0	0
T4	945335	322439	0	0
T8	5418	0	0	0
T9	3130	0	0	0
T20	2209	0	0	0
T21	1655	0	0	0
T22	1332	0	0	0
T23	1915	0	0	0
T26	940	0	0	0
T38	0	128596	0	0
T68	0	52204	0	0
T94	0	349519	0	0
T96	0	145601	0	0
T221	0	205639	0	0
T222	0	154347	0	0
T223	0	54335	0	0
T224	0	100196	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209425837	43020	0	0
T4	945335	9087	0	0
T8	5418	0	0	0
T9	3130	0	0	0
T15	2364	0	0	0
T23	1915	0	0	0
T24	1536	0	0	0
T26	940	0	0	0
T29	855	0	0	0
T40	1999	0	0	0
T47	1314	0	0	0
T96	0	4512	0	0
T224	0	1422	0	0
T225	0	1410	0	0
T226	0	3928	0	0
T227	0	2383	0	0
T228	0	3918	0	0
T229	0	3393	0	0
T230	0	2634	0	0
T231	0	1756	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209425837	49678	0	0
T4	945335	10574	0	0
T8	5418	0	0	0
T9	3130	0	0	0
T15	2364	0	0	0
T23	1915	0	0	0
T24	1536	0	0	0
T26	940	0	0	0
T29	855	0	0	0
T40	1999	0	0	0
T47	1314	0	0	0
T96	0	4923	0	0
T224	0	1575	0	0
T225	0	1322	0	0
T226	0	4594	0	0
T227	0	2592	0	0
T228	0	4575	0	0
T229	0	4105	0	0
T230	0	2986	0	0
T231	0	1856	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209425837	42840	0	0
T3	3050	5	0	0
T4	945335	8997	0	0
T8	5418	0	0	0
T9	3130	0	0	0
T15	0	5	0	0
T20	2209	0	0	0
T21	1655	7	0	0
T22	1332	0	0	0
T23	1915	0	0	0
T26	940	0	0	0
T40	1999	0	0	0
T96	0	4302	0	0
T182	0	5	0	0
T224	0	1453	0	0
T225	0	1318	0	0
T232	0	3	0	0
T233	0	3	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209425837	50323	0	0
T4	945335	10637	0	0
T8	5418	0	0	0
T9	3130	0	0	0
T15	2364	0	0	0
T23	1915	0	0	0
T24	1536	0	0	0
T26	940	0	0	0
T29	855	0	0	0
T40	1999	0	0	0
T47	1314	0	0	0
T96	0	5050	0	0
T224	0	1775	0	0
T225	0	1534	0	0
T226	0	4464	0	0
T227	0	2790	0	0
T228	0	4230	0	0
T229	0	4155	0	0
T230	0	3075	0	0
T231	0	1862	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209425837	50236	0	0
T4	945335	9652	0	0
T8	5418	0	0	0
T9	3130	0	0	0
T15	2364	0	0	0
T23	1915	0	0	0
T24	1536	0	0	0
T26	940	0	0	0
T29	855	0	0	0
T40	1999	0	0	0
T47	1314	0	0	0
T48	0	21	0	0
T62	0	19	0	0
T96	0	4415	0	0
T224	0	1723	0	0
T225	0	1703	0	0
T226	0	4387	0	0
T234	0	29	0	0
T235	0	42	0	0
T236	0	70	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209425837	43935	0	0
T4	945335	9558	0	0
T8	5418	0	0	0
T9	3130	0	0	0
T15	2364	0	0	0
T23	1915	0	0	0
T24	1536	0	0	0
T26	940	0	0	0
T29	855	0	0	0
T40	1999	0	0	0
T47	1314	0	0	0
T96	0	4341	0	0
T224	0	1459	0	0
T225	0	1311	0	0
T226	0	3746	0	0
T227	0	2129	0	0
T228	0	4037	0	0
T229	0	3397	0	0
T230	0	2483	0	0
T231	0	1575	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209425837	50580	0	0
T4	945335	10369	0	0
T8	5418	0	0	0
T9	3130	0	0	0
T15	2364	0	0	0
T23	1915	0	0	0
T24	1536	0	0	0
T26	940	0	0	0
T29	855	0	0	0
T40	1999	0	0	0
T47	1314	0	0	0
T96	0	5100	0	0
T224	0	1723	0	0
T225	0	1517	0	0
T226	0	4470	0	0
T227	0	2577	0	0
T228	0	4620	0	0
T229	0	4160	0	0
T230	0	3025	0	0
T231	0	1779	0	0