Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.28	98.25	93.85	91.61	91.86	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	88.82	99.92	92.58	50.89	91.86	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T11,T22

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T17,T18
1	0	Covered	T2,T4,T6

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T4,T9	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T9,T5,T10	Yes	T9,T5,T10	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T4,T9	Yes	T1,T4,T9	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T5,T34,T35	Yes	T5,T34,T35	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
edn_i[1].edn_req	Yes	Yes	T12,T36,T37	Yes	T12,T36,T37	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T10,T22	Yes	T1,T10,T22	INPUT
edn_i[3].edn_req	Yes	Yes	T9,T10,T36	Yes	T9,T10,T36	INPUT
edn_i[4].edn_req	Yes	Yes	T38,T39,T19	Yes	T38,T39,T19	INPUT
edn_i[5].edn_req	Yes	Yes	T3,T11,T38	Yes	T3,T11,T38	INPUT
edn_i[6].edn_req	Yes	Yes	T19,T40,T41	Yes	T19,T40,T41	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T5,T12	Yes	T1,T9,T5	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T5,T12,T23	Yes	T5,T12,T23	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T9,T5	Yes	T1,T9,T5	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T12,T36,T37	Yes	T12,T36,T37	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T12,T40,T41	Yes	T12,T37,T42	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T12,T36,T37	Yes	T12,T36,T37	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T22,T43	Yes	T1,T22,T43	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T44,T40,T41	Yes	T10,T43,T44	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T10,T22	Yes	T1,T10,T22	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T10,T28,T44	Yes	T9,T10,T28	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T28,T45,T40	Yes	T9,T28,T44	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T9,T10,T36	Yes	T9,T10,T36	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T38,T39,T19	Yes	T38,T39,T19	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T41,T46,T47	Yes	T19,T41,T46	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T38,T39,T19	Yes	T38,T39,T19	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T11,T38,T44	Yes	T3,T11,T38	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T42,T40,T46	Yes	T38,T44,T42	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T3,T11,T38	Yes	T3,T11,T38	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T19,T40,T41	Yes	T19,T40,T41	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T19,T40,T48	Yes	T19,T40,T41	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T19,T40,T41	Yes	T19,T40,T41	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T9,T5,T10	Yes	T1,T9,T5	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T9,T5,T10	Yes	T9,T5,T10	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T22,T27,T49	Yes	T22,T27,T49	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T11,T22	Yes	T1,T11,T22	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T4,T50	Yes	T2,T4,T50	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T11,T22	Yes	T1,T11,T22	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T4,T50	Yes	T2,T4,T50	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T5,T23,T34	Yes	T5,T23,T34	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T5,T23,T34	Yes	T5,T23,T34	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	227424630	227222806	0	0
CsrngAppIfOut_A	227424630	227222806	0	0
FpvSecCmCntAlertCheck_A	227424630	134	0	0
FpvSecCmGenCmdFifoRptrCheck_A	227424630	90	0	0
FpvSecCmGenCmdFifoWptrCheck_A	227424630	90	0	0
FpvSecCmMainFsmCheck_A	227424630	90	0	0
FpvSecCmRegWeOnehotCheck_A	227424630	90	0	0
FpvSecCmResCmdFifoRptrCheck_A	227424630	90	0	0
FpvSecCmResCmdFifoWptrCheck_A	227424630	90	0	0
IntrEdnCmdReqDoneKnownO_A	227424630	227222806	0	0
TlAReadyKnownO_A	227424630	227222806	0	0
TlDValidKnownO_A	227424630	227222806	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	227424630	90	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	227424630	90	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	227424630	90	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	227424630	90	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	227424630	90	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	227424630	90	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	227424630	90	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	227424630	601761	0	320
gen_edn_if_asserts[0].EdnDataStable_A	227424630	21596	0	423
gen_edn_if_asserts[0].EdnEndPointOut_A	227424630	227222806	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	227424630	167152	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	227424630	601761	0	320
gen_edn_if_asserts[1].EdnDataStable_A	227424630	4034	0	136
gen_edn_if_asserts[1].EdnEndPointOut_A	227424630	227222806	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	227424630	167152	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	227424630	601761	0	320
gen_edn_if_asserts[2].EdnDataStable_A	227424630	3940	0	130
gen_edn_if_asserts[2].EdnEndPointOut_A	227424630	227222806	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	227424630	167152	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	227424630	601761	0	320
gen_edn_if_asserts[3].EdnDataStable_A	227424630	5020	0	105
gen_edn_if_asserts[3].EdnEndPointOut_A	227424630	227222806	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	227424630	167152	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	227424630	601761	0	320
gen_edn_if_asserts[4].EdnDataStable_A	227424630	2845	0	101
gen_edn_if_asserts[4].EdnEndPointOut_A	227424630	227222806	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	227424630	167152	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	227424630	601761	0	320
gen_edn_if_asserts[5].EdnDataStable_A	227424630	4580	0	96
gen_edn_if_asserts[5].EdnEndPointOut_A	227424630	227222806	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	227424630	167152	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	227424630	601761	0	320
gen_edn_if_asserts[6].EdnDataStable_A	227424630	3358	0	81
gen_edn_if_asserts[6].EdnEndPointOut_A	227424630	227222806	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	227424630	167152	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	227222806	0	0
T1	1845	1762	0	0
T2	1742	1606	0	0
T3	4690	4619	0	0
T4	25005	14523	0	0
T5	249098	249085	0	0
T9	2373	2289	0	0
T10	1369	1301	0	0
T11	1781	1724	0	0
T12	2045	1966	0	0
T22	1656	1590	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	227222806	0	0
T1	1845	1762	0	0
T2	1742	1606	0	0
T3	4690	4619	0	0
T4	25005	14523	0	0
T5	249098	249085	0	0
T9	2373	2289	0	0
T10	1369	1301	0	0
T11	1781	1724	0	0
T12	2045	1966	0	0
T22	1656	1590	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	134	0	0
T4	25005	10	0	0
T5	249098	0	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	1656	0	0	0
T23	33028	0	0	0
T27	2403	0	0	0
T36	2197	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	90	0	0
T4	25005	10	0	0
T5	249098	0	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	1656	0	0	0
T23	33028	0	0	0
T27	2403	0	0	0
T36	2197	0	0	0
T56	0	20	0	0
T57	0	20	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	90	0	0
T4	25005	10	0	0
T5	249098	0	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	1656	0	0	0
T23	33028	0	0	0
T27	2403	0	0	0
T36	2197	0	0	0
T56	0	20	0	0
T57	0	20	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	90	0	0
T4	25005	10	0	0
T5	249098	0	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	1656	0	0	0
T23	33028	0	0	0
T27	2403	0	0	0
T36	2197	0	0	0
T56	0	20	0	0
T57	0	20	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	90	0	0
T4	25005	10	0	0
T5	249098	0	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	1656	0	0	0
T23	33028	0	0	0
T27	2403	0	0	0
T36	2197	0	0	0
T56	0	20	0	0
T57	0	20	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	90	0	0
T4	25005	10	0	0
T5	249098	0	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	1656	0	0	0
T23	33028	0	0	0
T27	2403	0	0	0
T36	2197	0	0	0
T56	0	20	0	0
T57	0	20	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	90	0	0
T4	25005	10	0	0
T5	249098	0	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	1656	0	0	0
T23	33028	0	0	0
T27	2403	0	0	0
T36	2197	0	0	0
T56	0	20	0	0
T57	0	20	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	227222806	0	0
T1	1845	1762	0	0
T2	1742	1606	0	0
T3	4690	4619	0	0
T4	25005	14523	0	0
T5	249098	249085	0	0
T9	2373	2289	0	0
T10	1369	1301	0	0
T11	1781	1724	0	0
T12	2045	1966	0	0
T22	1656	1590	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	227222806	0	0
T1	1845	1762	0	0
T2	1742	1606	0	0
T3	4690	4619	0	0
T4	25005	14523	0	0
T5	249098	249085	0	0
T9	2373	2289	0	0
T10	1369	1301	0	0
T11	1781	1724	0	0
T12	2045	1966	0	0
T22	1656	1590	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	227222806	0	0
T1	1845	1762	0	0
T2	1742	1606	0	0
T3	4690	4619	0	0
T4	25005	14523	0	0
T5	249098	249085	0	0
T9	2373	2289	0	0
T10	1369	1301	0	0
T11	1781	1724	0	0
T12	2045	1966	0	0
T22	1656	1590	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	90	0	0
T4	25005	10	0	0
T5	249098	0	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	1656	0	0	0
T23	33028	0	0	0
T27	2403	0	0	0
T36	2197	0	0	0
T56	0	20	0	0
T57	0	20	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	90	0	0
T4	25005	10	0	0
T5	249098	0	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	1656	0	0	0
T23	33028	0	0	0
T27	2403	0	0	0
T36	2197	0	0	0
T56	0	20	0	0
T57	0	20	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	90	0	0
T4	25005	10	0	0
T5	249098	0	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	1656	0	0	0
T23	33028	0	0	0
T27	2403	0	0	0
T36	2197	0	0	0
T56	0	20	0	0
T57	0	20	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	90	0	0
T4	25005	10	0	0
T5	249098	0	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	1656	0	0	0
T23	33028	0	0	0
T27	2403	0	0	0
T36	2197	0	0	0
T56	0	20	0	0
T57	0	20	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	90	0	0
T4	25005	10	0	0
T5	249098	0	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	1656	0	0	0
T23	33028	0	0	0
T27	2403	0	0	0
T36	2197	0	0	0
T56	0	20	0	0
T57	0	20	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	90	0	0
T4	25005	10	0	0
T5	249098	0	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	1656	0	0	0
T23	33028	0	0	0
T27	2403	0	0	0
T36	2197	0	0	0
T56	0	20	0	0
T57	0	20	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	90	0	0
T4	25005	10	0	0
T5	249098	0	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T17	0	20	0	0
T18	0	20	0	0
T22	1656	0	0	0
T23	33028	0	0	0
T27	2403	0	0	0
T36	2197	0	0	0
T56	0	20	0	0
T57	0	20	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	601761	0	320
T1	1845	231	0	0
T2	1742	1004	0	0
T3	4690	14	0	0
T4	25005	11167	0	2
T5	249098	1442	0	2
T9	2373	778	0	2
T10	1369	319	0	2
T11	1781	139	0	0
T12	2045	77	0	0
T17	0	0	0	2
T22	1656	255	0	0
T34	0	0	0	2
T35	0	0	0	2
T36	0	0	0	2
T50	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	21596	0	423
T1	1845	4	0	0
T2	1742	0	0	0
T3	4690	0	0	0
T4	25005	0	0	0
T5	249098	87	0	0
T9	2373	4	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	48	0	1
T22	1656	0	0	0
T23	0	17	0	0
T27	0	4	0	1
T34	0	72	0	0
T37	0	0	0	1
T38	0	0	0	1
T49	0	0	0	1
T59	0	34	0	1
T60	0	3	0	1
T61	0	12	0	1
T62	0	0	0	1
T63	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	227222806	0	0
T1	1845	1762	0	0
T2	1742	1606	0	0
T3	4690	4619	0	0
T4	25005	14523	0	0
T5	249098	249085	0	0
T9	2373	2289	0	0
T10	1369	1301	0	0
T11	1781	1724	0	0
T12	2045	1966	0	0
T22	1656	1590	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	167152	0	0
T2	1742	1082	0	0
T3	4690	0	0	0
T4	25005	9110	0	0
T5	249098	0	0	0
T6	0	1102	0	0
T7	0	259	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T15	0	1070	0	0
T16	0	464	0	0
T22	1656	0	0	0
T36	2197	0	0	0
T51	0	396	0	0
T64	0	612	0	0
T65	0	1140	0	0
T66	0	1123	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	601761	0	320
T1	1845	231	0	0
T2	1742	1004	0	0
T3	4690	14	0	0
T4	25005	11167	0	2
T5	249098	1442	0	2
T9	2373	778	0	2
T10	1369	319	0	2
T11	1781	139	0	0
T12	2045	77	0	0
T17	0	0	0	2
T22	1656	255	0	0
T34	0	0	0	2
T35	0	0	0	2
T36	0	0	0	2
T50	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	4034	0	136
T12	2045	15	0	1
T22	1656	0	0	0
T23	33028	0	0	0
T27	2403	0	0	0
T34	301543	0	0	0
T36	2197	4	0	0
T37	0	3	0	1
T40	0	11	0	1
T41	0	50	0	1
T42	0	3	0	1
T44	0	3	0	1
T46	0	3	0	1
T50	1078	0	0	0
T59	1441	0	0	0
T60	1598	0	0	0
T61	21483	0	0	0
T67	0	4	0	1
T68	0	4	0	0
T69	0	0	0	1
T70	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	227222806	0	0
T1	1845	1762	0	0
T2	1742	1606	0	0
T3	4690	4619	0	0
T4	25005	14523	0	0
T5	249098	249085	0	0
T9	2373	2289	0	0
T10	1369	1301	0	0
T11	1781	1724	0	0
T12	2045	1966	0	0
T22	1656	1590	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	167152	0	0
T2	1742	1082	0	0
T3	4690	0	0	0
T4	25005	9110	0	0
T5	249098	0	0	0
T6	0	1102	0	0
T7	0	259	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T15	0	1070	0	0
T16	0	464	0	0
T22	1656	0	0	0
T36	2197	0	0	0
T51	0	396	0	0
T64	0	612	0	0
T65	0	1140	0	0
T66	0	1123	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	601761	0	320
T1	1845	231	0	0
T2	1742	1004	0	0
T3	4690	14	0	0
T4	25005	11167	0	2
T5	249098	1442	0	2
T9	2373	778	0	2
T10	1369	319	0	2
T11	1781	139	0	0
T12	2045	77	0	0
T17	0	0	0	2
T22	1656	255	0	0
T34	0	0	0	2
T35	0	0	0	2
T36	0	0	0	2
T50	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	3940	0	130
T1	1845	4	0	1
T2	1742	0	0	0
T3	4690	0	0	0
T4	25005	0	0	0
T5	249098	0	0	0
T9	2373	0	0	0
T10	1369	3	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T21	0	0	0	1
T22	1656	4	0	1
T40	0	46	0	1
T41	0	49	0	1
T43	0	4	0	1
T44	0	46	0	1
T51	0	1	0	0
T71	0	69	0	1
T72	0	1	0	0
T73	0	0	0	1
T74	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	227222806	0	0
T1	1845	1762	0	0
T2	1742	1606	0	0
T3	4690	4619	0	0
T4	25005	14523	0	0
T5	249098	249085	0	0
T9	2373	2289	0	0
T10	1369	1301	0	0
T11	1781	1724	0	0
T12	2045	1966	0	0
T22	1656	1590	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	167152	0	0
T2	1742	1082	0	0
T3	4690	0	0	0
T4	25005	9110	0	0
T5	249098	0	0	0
T6	0	1102	0	0
T7	0	259	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T15	0	1070	0	0
T16	0	464	0	0
T22	1656	0	0	0
T36	2197	0	0	0
T51	0	396	0	0
T64	0	612	0	0
T65	0	1140	0	0
T66	0	1123	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	601761	0	320
T1	1845	231	0	0
T2	1742	1004	0	0
T3	4690	14	0	0
T4	25005	11167	0	2
T5	249098	1442	0	2
T9	2373	778	0	2
T10	1369	319	0	2
T11	1781	139	0	0
T12	2045	77	0	0
T17	0	0	0	2
T22	1656	255	0	0
T34	0	0	0	2
T35	0	0	0	2
T36	0	0	0	2
T50	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	5020	0	105
T5	249098	0	0	0
T9	2373	1	0	0
T10	1369	4	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T21	0	0	0	1
T22	1656	0	0	0
T23	33028	0	0	0
T27	2403	0	0	0
T28	0	1	0	0
T36	2197	1	0	0
T40	0	28	0	1
T41	0	3	0	1
T42	0	3	0	1
T44	0	3	0	1
T45	0	33	0	1
T46	0	35	0	1
T48	0	0	0	1
T59	1441	0	0	0
T73	0	0	0	1
T74	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	227222806	0	0
T1	1845	1762	0	0
T2	1742	1606	0	0
T3	4690	4619	0	0
T4	25005	14523	0	0
T5	249098	249085	0	0
T9	2373	2289	0	0
T10	1369	1301	0	0
T11	1781	1724	0	0
T12	2045	1966	0	0
T22	1656	1590	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	167152	0	0
T2	1742	1082	0	0
T3	4690	0	0	0
T4	25005	9110	0	0
T5	249098	0	0	0
T6	0	1102	0	0
T7	0	259	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T15	0	1070	0	0
T16	0	464	0	0
T22	1656	0	0	0
T36	2197	0	0	0
T51	0	396	0	0
T64	0	612	0	0
T65	0	1140	0	0
T66	0	1123	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	601761	0	320
T1	1845	231	0	0
T2	1742	1004	0	0
T3	4690	14	0	0
T4	25005	11167	0	2
T5	249098	1442	0	2
T9	2373	778	0	2
T10	1369	319	0	2
T11	1781	139	0	0
T12	2045	77	0	0
T17	0	0	0	2
T22	1656	255	0	0
T34	0	0	0	2
T35	0	0	0	2
T36	0	0	0	2
T50	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	2845	0	101
T16	834	0	0	0
T19	1608	15	0	1
T37	4538	0	0	0
T38	2061	12	0	1
T39	2606	4	0	1
T40	0	4	0	1
T41	0	33	0	1
T42	0	3	0	1
T46	0	43	0	1
T47	0	0	0	1
T51	1045	0	0	0
T53	0	1	0	0
T63	2779	0	0	0
T64	1116	0	0	0
T65	2008	0	0	0
T73	0	3	0	1
T75	0	4	0	1
T76	934	0	0	0

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	227222806	0	0
T1	1845	1762	0	0
T2	1742	1606	0	0
T3	4690	4619	0	0
T4	25005	14523	0	0
T5	249098	249085	0	0
T9	2373	2289	0	0
T10	1369	1301	0	0
T11	1781	1724	0	0
T12	2045	1966	0	0
T22	1656	1590	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	167152	0	0
T2	1742	1082	0	0
T3	4690	0	0	0
T4	25005	9110	0	0
T5	249098	0	0	0
T6	0	1102	0	0
T7	0	259	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T15	0	1070	0	0
T16	0	464	0	0
T22	1656	0	0	0
T36	2197	0	0	0
T51	0	396	0	0
T64	0	612	0	0
T65	0	1140	0	0
T66	0	1123	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	601761	0	320
T1	1845	231	0	0
T2	1742	1004	0	0
T3	4690	14	0	0
T4	25005	11167	0	2
T5	249098	1442	0	2
T9	2373	778	0	2
T10	1369	319	0	2
T11	1781	139	0	0
T12	2045	77	0	0
T17	0	0	0	2
T22	1656	255	0	0
T34	0	0	0	2
T35	0	0	0	2
T36	0	0	0	2
T50	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	4580	0	96
T3	4690	3	0	1
T4	25005	0	0	0
T5	249098	0	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	4	0	1
T12	2045	0	0	0
T21	0	3	0	1
T22	1656	0	0	0
T27	2403	0	0	0
T36	2197	0	0	0
T38	0	8	0	1
T40	0	57	0	1
T41	0	3	0	1
T42	0	44	0	1
T44	0	3	0	1
T46	0	34	0	1
T73	0	3	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	227222806	0	0
T1	1845	1762	0	0
T2	1742	1606	0	0
T3	4690	4619	0	0
T4	25005	14523	0	0
T5	249098	249085	0	0
T9	2373	2289	0	0
T10	1369	1301	0	0
T11	1781	1724	0	0
T12	2045	1966	0	0
T22	1656	1590	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	167152	0	0
T2	1742	1082	0	0
T3	4690	0	0	0
T4	25005	9110	0	0
T5	249098	0	0	0
T6	0	1102	0	0
T7	0	259	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T15	0	1070	0	0
T16	0	464	0	0
T22	1656	0	0	0
T36	2197	0	0	0
T51	0	396	0	0
T64	0	612	0	0
T65	0	1140	0	0
T66	0	1123	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	601761	0	320
T1	1845	231	0	0
T2	1742	1004	0	0
T3	4690	14	0	0
T4	25005	11167	0	2
T5	249098	1442	0	2
T9	2373	778	0	2
T10	1369	319	0	2
T11	1781	139	0	0
T12	2045	77	0	0
T17	0	0	0	2
T22	1656	255	0	0
T34	0	0	0	2
T35	0	0	0	2
T36	0	0	0	2
T50	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	3358	0	81
T7	2243	0	0	0
T19	1608	9	0	1
T21	0	3	0	1
T28	1616	0	0	0
T29	1992	0	0	0
T40	0	47	0	1
T41	0	3	0	1
T44	1787	0	0	0
T46	0	3	0	1
T48	0	31	0	1
T52	2981	0	0	0
T66	2973	0	0	0
T73	0	6	0	1
T77	0	3	0	1
T78	0	4	0	0
T79	0	22	0	1
T80	24670	0	0	0
T81	3406	0	0	0
T82	1013	0	0	0
T83	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	227222806	0	0
T1	1845	1762	0	0
T2	1742	1606	0	0
T3	4690	4619	0	0
T4	25005	14523	0	0
T5	249098	249085	0	0
T9	2373	2289	0	0
T10	1369	1301	0	0
T11	1781	1724	0	0
T12	2045	1966	0	0
T22	1656	1590	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227424630	167152	0	0
T2	1742	1082	0	0
T3	4690	0	0	0
T4	25005	9110	0	0
T5	249098	0	0	0
T6	0	1102	0	0
T7	0	259	0	0
T9	2373	0	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T15	0	1070	0	0
T16	0	464	0	0
T22	1656	0	0	0
T36	2197	0	0	0
T51	0	396	0	0
T64	0	612	0	0
T65	0	1140	0	0
T66	0	1123	0	0