Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	227897285	9241139	0	0
boot_gen_cmd_rd_A	227897285	107411	0	0
boot_ins_cmd_rd_A	227897285	120938	0	0
ctrl_rd_A	227897285	108698	0	0
err_code_test_rd_A	227897285	121004	0	0
intr_enable_rd_A	227897285	117015	0	0
max_num_reqs_between_reseeds_rd_A	227897285	106583	0	0
regwen_rd_A	227897285	121795	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227897285	9241139	0	0
T5	249098	104083	0	0
T10	1369	0	0	0
T11	1781	0	0	0
T12	2045	0	0	0
T22	1656	0	0	0
T23	33028	0	0	0
T27	2403	0	0	0
T34	0	121517	0	0
T35	0	72433	0	0
T36	2197	0	0	0
T59	1441	0	0	0
T60	1598	0	0	0
T89	0	424632	0	0
T90	0	276985	0	0
T92	0	374793	0	0
T223	0	85129	0	0
T224	0	120454	0	0
T225	0	286719	0	0
T226	0	120960	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227897285	107411	0	0
T69	1531	0	0	0
T70	1485	0	0	0
T75	2345	0	0	0
T90	485366	0	0	0
T91	1201	0	0	0
T92	106328	11158	0	0
T94	2002	0	0	0
T97	2647	0	0	0
T225	0	4204	0	0
T226	0	3495	0	0
T227	0	7541	0	0
T228	0	3722	0	0
T229	0	1741	0	0
T230	0	4630	0	0
T231	0	11777	0	0
T232	0	7440	0	0
T233	0	3356	0	0
T234	1453	0	0	0
T235	1742	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227897285	120938	0	0
T69	1531	0	0	0
T70	1485	0	0	0
T75	2345	0	0	0
T90	485366	0	0	0
T91	1201	0	0	0
T92	106328	12812	0	0
T94	2002	0	0	0
T97	2647	0	0	0
T225	0	4698	0	0
T226	0	3989	0	0
T227	0	8777	0	0
T228	0	4112	0	0
T229	0	1920	0	0
T230	0	4822	0	0
T231	0	13415	0	0
T232	0	8621	0	0
T233	0	3686	0	0
T234	1453	0	0	0
T235	1742	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227897285	108698	0	0
T7	2243	0	0	0
T19	1608	0	0	0
T24	0	7	0	0
T28	1616	0	0	0
T29	1992	0	0	0
T30	0	1	0	0
T39	2606	0	0	0
T51	1045	3	0	0
T52	2981	0	0	0
T58	0	2	0	0
T65	2008	0	0	0
T66	2973	0	0	0
T80	24670	0	0	0
T92	0	11272	0	0
T225	0	4144	0	0
T226	0	3397	0	0
T227	0	7501	0	0
T228	0	3701	0	0
T229	0	1780	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227897285	121004	0	0
T69	1531	0	0	0
T70	1485	0	0	0
T75	2345	0	0	0
T90	485366	0	0	0
T91	1201	0	0	0
T92	106328	12417	0	0
T94	2002	0	0	0
T97	2647	0	0	0
T225	0	5028	0	0
T226	0	3739	0	0
T227	0	8613	0	0
T228	0	4302	0	0
T229	0	1904	0	0
T230	0	5120	0	0
T231	0	13079	0	0
T232	0	7993	0	0
T233	0	3825	0	0
T234	1453	0	0	0
T235	1742	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227897285	117015	0	0
T41	2147	0	0	0
T46	3779	0	0	0
T58	20564	62	0	0
T68	2454	0	0	0
T71	4089	0	0	0
T72	796	0	0	0
T92	0	11904	0	0
T95	1021	0	0	0
T96	880	0	0	0
T225	0	4713	0	0
T226	0	3959	0	0
T227	0	7508	0	0
T228	0	3969	0	0
T236	0	82	0	0
T237	0	1	0	0
T238	0	13	0	0
T239	0	15	0	0
T240	882	0	0	0
T241	19551	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227897285	106583	0	0
T69	1531	0	0	0
T70	1485	0	0	0
T75	2345	0	0	0
T90	485366	0	0	0
T91	1201	0	0	0
T92	106328	10906	0	0
T94	2002	0	0	0
T97	2647	0	0	0
T225	0	4065	0	0
T226	0	3426	0	0
T227	0	7417	0	0
T228	0	3854	0	0
T229	0	1463	0	0
T230	0	4466	0	0
T231	0	12174	0	0
T232	0	7601	0	0
T233	0	2881	0	0
T234	1453	0	0	0
T235	1742	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227897285	121795	0	0
T69	1531	0	0	0
T70	1485	0	0	0
T75	2345	0	0	0
T90	485366	0	0	0
T91	1201	0	0	0
T92	106328	12780	0	0
T94	2002	0	0	0
T97	2647	0	0	0
T225	0	5165	0	0
T226	0	3855	0	0
T227	0	8603	0	0
T228	0	4368	0	0
T229	0	2074	0	0
T230	0	5381	0	0
T231	0	13221	0	0
T232	0	8230	0	0
T233	0	3519	0	0
T234	1453	0	0	0
T235	1742	0	0	0