Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	223876503	10156869	0	0
boot_gen_cmd_rd_A	223876503	41122	0	0
boot_ins_cmd_rd_A	223876503	46433	0	0
ctrl_rd_A	223876503	41025	0	0
err_code_test_rd_A	223876503	46453	0	0
intr_enable_rd_A	223876503	46474	0	0
max_num_reqs_between_reseeds_rd_A	223876503	42276	0	0
regwen_rd_A	223876503	47585	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223876503	10156869	0	0
T2	150131	51336	0	0
T3	5144	0	0	0
T5	0	529454	0	0
T9	2113	0	0	0
T10	1480	0	0	0
T18	2169	0	0	0
T23	1464	0	0	0
T24	1516	0	0	0
T25	2358	0	0	0
T26	2149	0	0	0
T38	0	221116	0	0
T75	2299	0	0	0
T219	0	238046	0	0
T220	0	113218	0	0
T221	0	65174	0	0
T222	0	231287	0	0
T223	0	305876	0	0
T224	0	515982	0	0
T225	0	426186	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223876503	41122	0	0
T2	150131	1595	0	0
T3	5144	0	0	0
T9	2113	0	0	0
T10	1480	0	0	0
T18	2169	0	0	0
T23	1464	0	0	0
T24	1516	0	0	0
T25	2358	0	0	0
T26	2149	0	0	0
T75	2299	0	0	0
T222	0	6348	0	0
T226	0	2491	0	0
T227	0	2178	0	0
T228	0	1952	0	0
T229	0	3954	0	0
T230	0	2925	0	0
T231	0	2145	0	0
T232	0	2613	0	0
T233	0	1300	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223876503	46433	0	0
T2	150131	1633	0	0
T3	5144	0	0	0
T9	2113	0	0	0
T10	1480	0	0	0
T18	2169	0	0	0
T23	1464	0	0	0
T24	1516	0	0	0
T25	2358	0	0	0
T26	2149	0	0	0
T75	2299	0	0	0
T222	0	7252	0	0
T226	0	2608	0	0
T227	0	2190	0	0
T228	0	2259	0	0
T229	0	4981	0	0
T230	0	3391	0	0
T231	0	2396	0	0
T232	0	2991	0	0
T233	0	1507	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223876503	41025	0	0
T2	150131	1375	0	0
T3	5144	0	0	0
T9	2113	0	0	0
T10	1480	0	0	0
T18	2169	0	0	0
T23	1464	0	0	0
T24	1516	0	0	0
T25	2358	0	0	0
T26	2149	0	0	0
T71	0	6	0	0
T75	2299	0	0	0
T80	0	4	0	0
T127	0	5	0	0
T222	0	6704	0	0
T226	0	2404	0	0
T234	0	5	0	0
T235	0	2	0	0
T236	0	4	0	0
T237	0	8	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223876503	46453	0	0
T2	150131	1686	0	0
T3	5144	0	0	0
T9	2113	0	0	0
T10	1480	0	0	0
T18	2169	0	0	0
T23	1464	0	0	0
T24	1516	0	0	0
T25	2358	0	0	0
T26	2149	0	0	0
T75	2299	0	0	0
T222	0	7344	0	0
T226	0	2590	0	0
T227	0	2366	0	0
T228	0	1995	0	0
T229	0	4889	0	0
T230	0	3142	0	0
T231	0	2371	0	0
T232	0	3064	0	0
T233	0	1533	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223876503	46474	0	0
T2	150131	1779	0	0
T3	5144	0	0	0
T9	2113	0	0	0
T10	1480	0	0	0
T18	2169	0	0	0
T23	1464	0	0	0
T24	1516	0	0	0
T25	2358	0	0	0
T26	2149	0	0	0
T64	0	72	0	0
T75	2299	0	0	0
T107	0	16	0	0
T222	0	7035	0	0
T226	0	2775	0	0
T227	0	2125	0	0
T235	0	66	0	0
T237	0	4	0	0
T238	0	24	0	0
T239	0	31	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223876503	42276	0	0
T2	150131	1514	0	0
T3	5144	0	0	0
T9	2113	0	0	0
T10	1480	0	0	0
T18	2169	0	0	0
T23	1464	0	0	0
T24	1516	0	0	0
T25	2358	0	0	0
T26	2149	0	0	0
T75	2299	0	0	0
T222	0	6323	0	0
T226	0	2707	0	0
T227	0	2292	0	0
T228	0	2009	0	0
T229	0	4313	0	0
T230	0	2800	0	0
T231	0	2070	0	0
T232	0	2719	0	0
T233	0	1229	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223876503	47585	0	0
T2	150131	1527	0	0
T3	5144	0	0	0
T9	2113	0	0	0
T10	1480	0	0	0
T18	2169	0	0	0
T23	1464	0	0	0
T24	1516	0	0	0
T25	2358	0	0	0
T26	2149	0	0	0
T75	2299	0	0	0
T222	0	7910	0	0
T226	0	2811	0	0
T227	0	2066	0	0
T228	0	2249	0	0
T229	0	5089	0	0
T230	0	3138	0	0
T231	0	2104	0	0
T232	0	3064	0	0
T233	0	1508	0	0