Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	98.25	93.97	97.02	92.44	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.23	99.92	92.75	82.54	92.44	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T18,T9,T24

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T19,T20
1	0	Covered	T4,T6,T7

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T9	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T2,T5,T38	Yes	T2,T5,T38	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T3,T30	Yes	T1,T3,T30	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T3,T18	Yes	T1,T3,T18	INPUT
edn_i[3].edn_req	Yes	Yes	T1,T3,T11	Yes	T1,T3,T11	INPUT
edn_i[4].edn_req	Yes	Yes	T1,T21,T22	Yes	T1,T21,T22	INPUT
edn_i[5].edn_req	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	INPUT
edn_i[6].edn_req	Yes	Yes	T3,T14,T22	Yes	T3,T14,T22	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T9,T23	Yes	T1,T2,T9	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T2,T23,T10	Yes	T2,T23,T10	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T1,T3,T30	Yes	T1,T3,T30	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T1,T3,T30	Yes	T1,T3,T30	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T3,T30	Yes	T1,T3,T30	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T3,T18	Yes	T1,T3,T18	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T1,T3,T30	Yes	T1,T3,T18	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T3,T18	Yes	T1,T3,T18	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T1,T3,T11	Yes	T1,T3,T11	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T1,T3,T11	Yes	T1,T3,T11	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T1,T3,T11	Yes	T1,T3,T11	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T1,T21,T22	Yes	T1,T21,T22	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T12,T41,T42	Yes	T1,T21,T22	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T1,T21,T22	Yes	T1,T21,T22	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T39,T43,T12	Yes	T1,T39,T40	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T12,T44,T45	Yes	T1,T12,T44	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T1,T39,T40	Yes	T1,T39,T40	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T3,T14,T46	Yes	T3,T14,T46	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T3,T46,T39	Yes	T3,T46,T39	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T3,T14,T22	Yes	T3,T14,T22	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T18,T9,T25	Yes	T18,T9,T25	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T9,T24	Yes	T18,T9,T24	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T47,T4,T6	Yes	T47,T4,T6	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T9,T24	Yes	T18,T9,T24	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T47,T4,T6	Yes	T47,T4,T6	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T2,T5,T48	Yes	T2,T5,T48	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T2,T5,T48	Yes	T2,T5,T48	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	223367997	223178455	0	0
CsrngAppIfOut_A	223367997	223178455	0	0
FpvSecCmCntAlertCheck_A	223367997	120	0	0
FpvSecCmGenCmdFifoRptrCheck_A	223367997	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	223367997	80	0	0
FpvSecCmMainFsmCheck_A	223367997	80	0	0
FpvSecCmRegWeOnehotCheck_A	223367997	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	223367997	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	223367997	80	0	0
IntrEdnCmdReqDoneKnownO_A	223367997	223178455	0	0
TlAReadyKnownO_A	223367997	223178455	0	0
TlDValidKnownO_A	223367997	223178455	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	223367997	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	223367997	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	223367997	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	223367997	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	223367997	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	223367997	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	223367997	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	223367997	613422	0	328
gen_edn_if_asserts[0].EdnDataStable_A	223367997	175276	0	433
gen_edn_if_asserts[0].EdnEndPointOut_A	223367997	223178455	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	223367997	153439	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	223367997	613422	0	328
gen_edn_if_asserts[1].EdnDataStable_A	223367997	6177	0	127
gen_edn_if_asserts[1].EdnEndPointOut_A	223367997	223178455	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	223367997	153439	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	223367997	613422	0	328
gen_edn_if_asserts[2].EdnDataStable_A	223367997	4569	0	115
gen_edn_if_asserts[2].EdnEndPointOut_A	223367997	223178455	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	223367997	153439	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	223367997	613422	0	328
gen_edn_if_asserts[3].EdnDataStable_A	223367997	4344	0	104
gen_edn_if_asserts[3].EdnEndPointOut_A	223367997	223178455	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	223367997	153439	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	223367997	613422	0	328
gen_edn_if_asserts[4].EdnDataStable_A	223367997	1907	0	104
gen_edn_if_asserts[4].EdnEndPointOut_A	223367997	223178455	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	223367997	153439	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	223367997	613422	0	328
gen_edn_if_asserts[5].EdnDataStable_A	223367997	52470	0	95
gen_edn_if_asserts[5].EdnEndPointOut_A	223367997	223178455	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	223367997	153439	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	223367997	613422	0	328
gen_edn_if_asserts[6].EdnDataStable_A	223367997	3713	0	96
gen_edn_if_asserts[6].EdnEndPointOut_A	223367997	223178455	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	223367997	153439	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	120	0	0
T15	496	1	0	0
T16	0	10	0	0
T17	0	1	0	0
T19	0	20	0	0
T27	1739	0	0	0
T32	1040	0	0	0
T33	637	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	1943	0	0	0
T56	790	0	0	0
T57	1263	0	0	0
T58	6094	0	0	0
T59	3988	0	0	0
T60	763	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	80	0	0
T16	21781	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T28	1773	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	946	0	0	0
T64	39377	0	0	0
T65	1904	0	0	0
T66	3401	0	0	0
T67	4239	0	0	0
T68	1836	0	0	0
T69	3639	0	0	0
T70	1999	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	80	0	0
T16	21781	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T28	1773	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	946	0	0	0
T64	39377	0	0	0
T65	1904	0	0	0
T66	3401	0	0	0
T67	4239	0	0	0
T68	1836	0	0	0
T69	3639	0	0	0
T70	1999	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	80	0	0
T16	21781	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T28	1773	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	946	0	0	0
T64	39377	0	0	0
T65	1904	0	0	0
T66	3401	0	0	0
T67	4239	0	0	0
T68	1836	0	0	0
T69	3639	0	0	0
T70	1999	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	80	0	0
T16	21781	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T28	1773	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	946	0	0	0
T64	39377	0	0	0
T65	1904	0	0	0
T66	3401	0	0	0
T67	4239	0	0	0
T68	1836	0	0	0
T69	3639	0	0	0
T70	1999	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	80	0	0
T16	21781	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T28	1773	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	946	0	0	0
T64	39377	0	0	0
T65	1904	0	0	0
T66	3401	0	0	0
T67	4239	0	0	0
T68	1836	0	0	0
T69	3639	0	0	0
T70	1999	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	80	0	0
T16	21781	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T28	1773	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	946	0	0	0
T64	39377	0	0	0
T65	1904	0	0	0
T66	3401	0	0	0
T67	4239	0	0	0
T68	1836	0	0	0
T69	3639	0	0	0
T70	1999	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	80	0	0
T16	21781	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T28	1773	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	946	0	0	0
T64	39377	0	0	0
T65	1904	0	0	0
T66	3401	0	0	0
T67	4239	0	0	0
T68	1836	0	0	0
T69	3639	0	0	0
T70	1999	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	80	0	0
T16	21781	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T28	1773	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	946	0	0	0
T64	39377	0	0	0
T65	1904	0	0	0
T66	3401	0	0	0
T67	4239	0	0	0
T68	1836	0	0	0
T69	3639	0	0	0
T70	1999	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	80	0	0
T16	21781	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T28	1773	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	946	0	0	0
T64	39377	0	0	0
T65	1904	0	0	0
T66	3401	0	0	0
T67	4239	0	0	0
T68	1836	0	0	0
T69	3639	0	0	0
T70	1999	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	80	0	0
T16	21781	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T28	1773	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	946	0	0	0
T64	39377	0	0	0
T65	1904	0	0	0
T66	3401	0	0	0
T67	4239	0	0	0
T68	1836	0	0	0
T69	3639	0	0	0
T70	1999	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	80	0	0
T16	21781	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T28	1773	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	946	0	0	0
T64	39377	0	0	0
T65	1904	0	0	0
T66	3401	0	0	0
T67	4239	0	0	0
T68	1836	0	0	0
T69	3639	0	0	0
T70	1999	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	80	0	0
T16	21781	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T28	1773	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	946	0	0	0
T64	39377	0	0	0
T65	1904	0	0	0
T66	3401	0	0	0
T67	4239	0	0	0
T68	1836	0	0	0
T69	3639	0	0	0
T70	1999	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	80	0	0
T16	21781	10	0	0
T19	0	20	0	0
T20	0	10	0	0
T28	1773	0	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	946	0	0	0
T64	39377	0	0	0
T65	1904	0	0	0
T66	3401	0	0	0
T67	4239	0	0	0
T68	1836	0	0	0
T69	3639	0	0	0
T70	1999	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	613422	0	328
T1	2809	172	0	0
T2	150131	1480	0	2
T3	5144	24	0	0
T5	0	0	0	2
T9	2113	184	0	0
T10	1480	75	0	0
T18	2169	191	0	0
T22	0	0	0	2
T23	1464	10	0	0
T24	1516	128	0	0
T25	2358	611	0	0
T26	2149	218	0	0
T38	0	0	0	2
T40	0	0	0	2
T47	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	175276	0	433
T1	2809	3	0	1
T2	150131	38	0	0
T3	5144	0	0	0
T9	2113	4	0	1
T10	1480	21	0	1
T18	2169	0	0	0
T23	1464	55	0	1
T24	1516	4	0	1
T25	2358	4	0	1
T26	2149	4	0	1
T75	0	4	0	1
T76	0	4	0	1
T77	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	153439	0	0
T4	2087	1118	0	0
T5	936650	0	0	0
T6	0	262	0	0
T7	0	670	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	204	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T31	0	7	0	0
T32	0	30	0	0
T33	0	24	0	0
T46	985	0	0	0
T77	2519	0	0	0
T78	0	663	0	0
T79	0	352	0	0
T80	0	912	0	0
T81	1896	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	613422	0	328
T1	2809	172	0	0
T2	150131	1480	0	2
T3	5144	24	0	0
T5	0	0	0	2
T9	2113	184	0	0
T10	1480	75	0	0
T18	2169	191	0	0
T22	0	0	0	2
T23	1464	10	0	0
T24	1516	128	0	0
T25	2358	611	0	0
T26	2149	218	0	0
T38	0	0	0	2
T40	0	0	0	2
T47	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	6177	0	127
T1	2809	20	0	1
T2	150131	0	0	0
T3	5144	28	0	1
T9	2113	0	0	0
T10	1480	0	0	0
T12	0	41	0	1
T18	2169	0	0	0
T23	1464	0	0	0
T24	1516	0	0	0
T25	2358	0	0	0
T26	2149	0	0	0
T30	0	64	0	1
T39	0	36	0	1
T41	0	60	0	1
T44	0	59	0	1
T58	0	423	0	1
T82	0	45	0	1
T83	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	153439	0	0
T4	2087	1118	0	0
T5	936650	0	0	0
T6	0	262	0	0
T7	0	670	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	204	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T31	0	7	0	0
T32	0	30	0	0
T33	0	24	0	0
T46	985	0	0	0
T77	2519	0	0	0
T78	0	663	0	0
T79	0	352	0	0
T80	0	912	0	0
T81	1896	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	613422	0	328
T1	2809	172	0	0
T2	150131	1480	0	2
T3	5144	24	0	0
T5	0	0	0	2
T9	2113	184	0	0
T10	1480	75	0	0
T18	2169	191	0	0
T22	0	0	0	2
T23	1464	10	0	0
T24	1516	128	0	0
T25	2358	611	0	0
T26	2149	218	0	0
T38	0	0	0	2
T40	0	0	0	2
T47	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	4569	0	115
T1	2809	49	0	1
T2	150131	0	0	0
T3	5144	41	0	1
T9	2113	0	0	0
T10	1480	0	0	0
T12	0	0	0	1
T14	0	4	0	0
T18	2169	4	0	1
T23	1464	0	0	0
T24	1516	0	0	0
T25	2358	0	0	0
T26	2149	0	0	0
T30	0	29	0	1
T44	0	0	0	1
T45	0	0	0	1
T75	0	4	0	0
T82	0	3	0	1
T84	0	3	0	1
T85	0	4	0	0
T86	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	153439	0	0
T4	2087	1118	0	0
T5	936650	0	0	0
T6	0	262	0	0
T7	0	670	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	204	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T31	0	7	0	0
T32	0	30	0	0
T33	0	24	0	0
T46	985	0	0	0
T77	2519	0	0	0
T78	0	663	0	0
T79	0	352	0	0
T80	0	912	0	0
T81	1896	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	613422	0	328
T1	2809	172	0	0
T2	150131	1480	0	2
T3	5144	24	0	0
T5	0	0	0	2
T9	2113	184	0	0
T10	1480	75	0	0
T18	2169	191	0	0
T22	0	0	0	2
T23	1464	10	0	0
T24	1516	128	0	0
T25	2358	611	0	0
T26	2149	218	0	0
T38	0	0	0	2
T40	0	0	0	2
T47	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	4344	0	104
T1	2809	207	0	1
T2	150131	0	0	0
T3	5144	17	0	1
T9	2113	0	0	0
T10	1480	0	0	0
T11	0	45	0	1
T12	0	3	0	1
T18	2169	0	0	0
T23	1464	0	0	0
T24	1516	0	0	0
T25	2358	0	0	0
T26	2149	0	0	0
T39	0	57	0	1
T41	0	3	0	1
T44	0	3	0	1
T59	0	50	0	1
T60	0	4	0	0
T86	0	3	0	1
T87	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	153439	0	0
T4	2087	1118	0	0
T5	936650	0	0	0
T6	0	262	0	0
T7	0	670	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	204	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T31	0	7	0	0
T32	0	30	0	0
T33	0	24	0	0
T46	985	0	0	0
T77	2519	0	0	0
T78	0	663	0	0
T79	0	352	0	0
T80	0	912	0	0
T81	1896	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	613422	0	328
T1	2809	172	0	0
T2	150131	1480	0	2
T3	5144	24	0	0
T5	0	0	0	2
T9	2113	184	0	0
T10	1480	75	0	0
T18	2169	191	0	0
T22	0	0	0	2
T23	1464	10	0	0
T24	1516	128	0	0
T25	2358	611	0	0
T26	2149	218	0	0
T38	0	0	0	2
T40	0	0	0	2
T47	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	1907	0	104
T1	2809	3	0	1
T2	150131	0	0	0
T3	5144	0	0	0
T9	2113	0	0	0
T10	1480	0	0	0
T12	0	32	0	1
T18	2169	0	0	0
T21	0	15	0	1
T22	0	4	0	0
T23	1464	0	0	0
T24	1516	0	0	0
T25	2358	0	0	0
T26	2149	0	0	0
T39	0	3	0	1
T41	0	54	0	1
T42	0	11	0	1
T44	0	11	0	1
T45	0	0	0	1
T71	0	4	0	0
T88	0	4	0	1
T89	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	153439	0	0
T4	2087	1118	0	0
T5	936650	0	0	0
T6	0	262	0	0
T7	0	670	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	204	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T31	0	7	0	0
T32	0	30	0	0
T33	0	24	0	0
T46	985	0	0	0
T77	2519	0	0	0
T78	0	663	0	0
T79	0	352	0	0
T80	0	912	0	0
T81	1896	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	613422	0	328
T1	2809	172	0	0
T2	150131	1480	0	2
T3	5144	24	0	0
T5	0	0	0	2
T9	2113	184	0	0
T10	1480	75	0	0
T18	2169	191	0	0
T22	0	0	0	2
T23	1464	10	0	0
T24	1516	128	0	0
T25	2358	611	0	0
T26	2149	218	0	0
T38	0	0	0	2
T40	0	0	0	2
T47	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	52470	0	95
T1	2809	4	0	1
T2	150131	0	0	0
T3	5144	0	0	0
T9	2113	0	0	0
T10	1480	0	0	0
T12	0	56	0	1
T13	0	0	0	1
T18	2169	0	0	0
T23	1464	0	0	0
T24	1516	0	0	0
T25	2358	0	0	0
T26	2149	0	0	0
T39	0	3	0	1
T40	0	4	0	0
T43	0	4	0	1
T44	0	24	0	1
T45	0	0	0	1
T59	0	11	0	1
T85	0	4	0	1
T88	0	4	0	0
T90	0	4	0	0
T91	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	153439	0	0
T4	2087	1118	0	0
T5	936650	0	0	0
T6	0	262	0	0
T7	0	670	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	204	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T31	0	7	0	0
T32	0	30	0	0
T33	0	24	0	0
T46	985	0	0	0
T77	2519	0	0	0
T78	0	663	0	0
T79	0	352	0	0
T80	0	912	0	0
T81	1896	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	613422	0	328
T1	2809	172	0	0
T2	150131	1480	0	2
T3	5144	24	0	0
T5	0	0	0	2
T9	2113	184	0	0
T10	1480	75	0	0
T18	2169	191	0	0
T22	0	0	0	2
T23	1464	10	0	0
T24	1516	128	0	0
T25	2358	611	0	0
T26	2149	218	0	0
T38	0	0	0	2
T40	0	0	0	2
T47	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	3713	0	96
T3	5144	20	0	1
T9	2113	0	0	0
T10	1480	0	0	0
T12	0	3	0	1
T14	0	4	0	1
T18	2169	0	0	0
T22	0	1	0	0
T23	1464	0	0	0
T24	1516	0	0	0
T25	2358	0	0	0
T26	2149	0	0	0
T39	0	58	0	1
T42	0	3	0	1
T44	0	3	0	1
T46	0	3	0	1
T47	957	0	0	0
T75	2299	0	0	0
T86	0	3	0	1
T92	0	4	0	1
T93	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	153439	0	0
T4	2087	1118	0	0
T5	936650	0	0	0
T6	0	262	0	0
T7	0	670	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	204	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T31	0	7	0	0
T32	0	30	0	0
T33	0	24	0	0
T46	985	0	0	0
T77	2519	0	0	0
T78	0	663	0	0
T79	0	352	0	0
T80	0	912	0	0
T81	1896	0	0	0