Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.60	100.00	94.44		95.95	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	94.44		95.95	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T46,T84
1	1	Covered	T18,T24,T25

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T25,T22,T81
1	1	Covered	T1,T18,T9

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T9,T24
1	0	Covered	T4,T6,T7

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T18,T9,T24
1	Covered	T4,T6,T7

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T18,T9,T24
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T18,T9,T24
1	Covered	T4,T6,T7

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T9,T24

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	71	95.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T1,T10,T14
AutoCaptGenCnt	143	Covered	T1,T10,T14
AutoCaptReseedCnt	141	Covered	T1,T10,T14
AutoDispatch	125	Covered	T1,T10,T14
AutoFirstAckWait	119	Covered	T1,T9,T10
AutoLoadIns	69	Covered	T1,T18,T9
AutoSendGenCmd	150	Covered	T1,T10,T14
AutoSendReseedCmd	162	Covered	T1,T10,T21
BootDone	98	Covered	T75,T4,T14
BootGenAckWait	90	Covered	T18,T25,T75
BootInsAckWait	80	Covered	T18,T24,T25
BootLoadGen	85	Covered	T18,T25,T75
BootLoadIns	65	Covered	T18,T24,T25
BootLoadUni	102	Covered	T75,T14,T30
BootPulse	94	Covered	T75,T4,T14
BootUniAckWait	107	Covered	T14,T30,T82
Error	188	Covered	T4,T6,T7
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T18,T9,T24
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T1,T10,T14
AutoAckWait->Error	188	Covered	T115,T116,T117
AutoAckWait->Idle	211	Covered	T22,T40,T71
AutoAckWait->RejectCsrngEntropy	188	Covered	T85,T92,T118
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T1,T10,T14
AutoCaptGenCnt->Error	188	Covered	T119,T120,T121
AutoCaptGenCnt->Idle	211	Covered	T67,T122,T123
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T124,T125,T126
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T1,T10,T21
AutoCaptReseedCnt->Error	188	Covered	T127,T128
AutoCaptReseedCnt->Idle	211	Covered	T129,T130,T131
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T14,T132,T133
AutoDispatch->AutoCaptGenCnt	143	Covered	T1,T10,T14
AutoDispatch->AutoCaptReseedCnt	141	Covered	T1,T10,T14
AutoDispatch->Error	188	Covered	T134,T135
AutoDispatch->Idle	138	Covered	T1,T10,T21
AutoDispatch->RejectCsrngEntropy	188	Covered	T136,T137,T138
AutoFirstAckWait->AutoDispatch	125	Covered	T1,T10,T14
AutoFirstAckWait->Error	188	Covered	T139
AutoFirstAckWait->Idle	211	Covered	T71,T140,T141
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T9,T113,T142
AutoLoadIns->AutoFirstAckWait	119	Covered	T1,T9,T10
AutoLoadIns->Error	188	Covered	T143,T144,T145
AutoLoadIns->Idle	211	Covered	T18,T75,T6
AutoLoadIns->RejectCsrngEntropy	188	Covered	T26,T146,T147
AutoSendGenCmd->AutoAckWait	156	Covered	T1,T10,T14
AutoSendGenCmd->Error	188	Covered	T8,T148,T149
AutoSendGenCmd->Idle	211	Covered	T22,T150,T151
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T81,T105,T152
AutoSendReseedCmd->AutoAckWait	168	Covered	T1,T10,T21
AutoSendReseedCmd->Error	188	Covered	T7,T153,T154
AutoSendReseedCmd->Idle	211	Covered	T66,T155,T156
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T157,T158,T159
BootDone->BootLoadUni	102	Covered	T75,T14,T30
BootDone->Error	188	Covered	T4,T160
BootDone->Idle	211	Covered	T161,T162,T163
BootDone->RejectCsrngEntropy	188	Covered	T88,T108,T109
BootGenAckWait->BootPulse	94	Covered	T75,T4,T14
BootGenAckWait->Error	188	Covered	T164
BootGenAckWait->Idle	211	Covered	T56,T165,T166
BootGenAckWait->RejectCsrngEntropy	188	Covered	T18,T25,T167
BootInsAckWait->BootLoadGen	85	Covered	T18,T25,T75
BootInsAckWait->Error	188	Covered	T78,T17,T50
BootInsAckWait->Idle	211	Covered	T4,T84,T78
BootInsAckWait->RejectCsrngEntropy	188	Covered	T24,T43,T168
BootLoadGen->BootGenAckWait	90	Covered	T18,T25,T75
BootLoadGen->Error	188	Not Covered
BootLoadGen->Idle	211	Covered	T169,T170,T171
BootLoadGen->RejectCsrngEntropy	188	Covered	T172,T173,T174
BootLoadIns->BootInsAckWait	80	Covered	T18,T24,T25
BootLoadIns->Error	188	Covered	T49,T175,T176
BootLoadIns->Idle	211	Covered	T93,T177,T178
BootLoadIns->RejectCsrngEntropy	188	Covered	T179,T180,T181
BootLoadUni->BootUniAckWait	107	Covered	T14,T30,T82
BootLoadUni->Error	188	Covered	T182
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T75,T183,T184
BootPulse->BootDone	98	Covered	T75,T4,T14
BootPulse->Error	188	Not Covered
BootPulse->Idle	211	Covered	T46,T83,T57
BootPulse->RejectCsrngEntropy	188	Covered	T185,T186,T187
BootUniAckWait->Error	188	Covered	T54,T188,T189
BootUniAckWait->Idle	112	Covered	T14,T30,T82
BootUniAckWait->RejectCsrngEntropy	188	Covered	T90,T65,T190
Idle->AutoLoadIns	69	Covered	T1,T18,T9
Idle->BootLoadIns	65	Covered	T18,T24,T25
Idle->Error	188	Covered	T16,T19,T20
Idle->RejectCsrngEntropy	188	Covered	T9,T25,T26
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T15,T191,T192
RejectCsrngEntropy->Idle	211	Covered	T18,T9,T24
SWPortMode->Error	188	Covered	T79,T80,T16
SWPortMode->Idle	211	Covered	T2,T9,T24
SWPortMode->RejectCsrngEntropy	188	Covered	T18,T24,T14

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T24,T25
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T9
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T24,T25
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T24,T25
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T18,T24,T25
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T25,T75
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T18,T25,T75
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T18,T25,T75
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T75,T4,T14
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T75,T14,T30
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T4,T14,T46
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T75,T14,T30
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T30,T82,T104
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T14,T30,T82
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T9,T10
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T18,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T10,T14
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T10,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T10,T21
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T10,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T10,T14
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T10,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T10,T14
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T10,T21
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T10,T21
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T9,T24
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T16,T100

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T4,T6,T7
1	0	1	-	Not Covered
1	0	0	-	Covered	T18,T9,T24
0	-	-	1	Covered	T18,T9,T24
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	223367997	148710	0	0
FpvSecCmErrorStEscalate_A	223367997	149880	0	0
u_state_regs_A	223329056	223139514	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	148710	0	0
T4	2087	1116	0	0
T5	936650	0	0	0
T6	0	210	0	0
T7	0	668	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	202	0	0
T16	0	7724	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T46	985	0	0	0
T68	0	1117	0	0
T77	2519	0	0	0
T78	0	661	0	0
T79	0	350	0	0
T80	0	910	0	0
T81	1896	0	0	0
T100	0	304	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	149880	0	0
T4	2087	1117	0	0
T5	936650	0	0	0
T6	0	211	0	0
T7	0	669	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	203	0	0
T16	0	7854	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T46	985	0	0	0
T68	0	1118	0	0
T77	2519	0	0	0
T78	0	662	0	0
T79	0	351	0	0
T80	0	911	0	0
T81	1896	0	0	0
T100	0	305	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223329056	223139514	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0