Module Definition
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Module : edn_core
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.31 100.00 91.03 98.23 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_edn_core 97.31 100.00 91.03 98.23 100.00



Module Instance : tb.dut.u_edn_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.31 100.00 91.03 98.23 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.23 99.92 92.75 82.54 92.44 98.83 98.88


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 83.33 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_ep_blk[0].u_edn_ack_sm_ep 98.57 100.00 100.00 92.86 100.00 100.00
gen_ep_blk[0].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[1].u_edn_ack_sm_ep 98.57 100.00 100.00 92.86 100.00 100.00
gen_ep_blk[1].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[2].u_edn_ack_sm_ep 98.57 100.00 100.00 92.86 100.00 100.00
gen_ep_blk[2].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[3].u_edn_ack_sm_ep 97.14 100.00 100.00 85.71 100.00 100.00
gen_ep_blk[3].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[4].u_edn_ack_sm_ep 97.14 100.00 100.00 85.71 100.00 100.00
gen_ep_blk[4].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[5].u_edn_ack_sm_ep 97.14 100.00 100.00 85.71 100.00 100.00
gen_ep_blk[5].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[6].u_edn_ack_sm_ep 98.57 100.00 100.00 92.86 100.00 100.00
gen_ep_blk[6].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
u_edn_main_sm 97.62 100.00 94.44 95.95 97.73 100.00
u_intr_hw_edn_cmd_req_done 100.00 100.00 100.00 100.00 100.00
u_intr_hw_edn_fatal_err 100.00 100.00 100.00 100.00 100.00
u_prim_arbiter_ppc_packer_arb 95.16 95.00 92.31 100.00 93.33
u_prim_count_max_reqs_cntr 70.79 70.79
u_prim_edge_detector_recov_alert 100.00 100.00 100.00 100.00
u_prim_fifo_sync_gencmd 98.38 100.00 91.89 100.00 100.00 100.00
u_prim_fifo_sync_rescmd 98.38 100.00 91.89 100.00 100.00 100.00
u_prim_mubi4_sync_auto_req_mode 100.00 100.00 100.00
u_prim_mubi4_sync_boot_req_mode 100.00 100.00 100.00
u_prim_mubi4_sync_cmd_fifo_rst 100.00 100.00 100.00
u_prim_mubi4_sync_edn_enable 100.00 100.00 100.00
u_prim_packer_fifo_cs 95.24 100.00 95.24 85.71 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : edn_core
Line No.TotalCoveredPercent
TOTAL262262100.00
ALWAYS2234040100.00
CONT_ASSIGN30211100.00
CONT_ASSIGN30711100.00
CONT_ASSIGN31411100.00
CONT_ASSIGN32011100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN32811100.00
CONT_ASSIGN33111100.00
CONT_ASSIGN33511100.00
CONT_ASSIGN33911100.00
CONT_ASSIGN34711100.00
CONT_ASSIGN35011100.00
CONT_ASSIGN35311100.00
CONT_ASSIGN35611100.00
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CONT_ASSIGN36111100.00
CONT_ASSIGN36211100.00
CONT_ASSIGN36711100.00
CONT_ASSIGN37011100.00
CONT_ASSIGN37311100.00
CONT_ASSIGN37811100.00
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CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
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CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
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CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
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CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38211100.00
CONT_ASSIGN38411100.00
CONT_ASSIGN38511100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN42311100.00
CONT_ASSIGN42411100.00
CONT_ASSIGN42511100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42911100.00
CONT_ASSIGN42911100.00
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CONT_ASSIGN42911100.00
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CONT_ASSIGN42911100.00
CONT_ASSIGN42911100.00
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CONT_ASSIGN42911100.00
CONT_ASSIGN44411100.00
CONT_ASSIGN44511100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45011100.00
CONT_ASSIGN45011100.00
CONT_ASSIGN45011100.00
CONT_ASSIGN46411100.00
CONT_ASSIGN47111100.00
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CONT_ASSIGN47311100.00
CONT_ASSIGN47411100.00
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CONT_ASSIGN49611100.00
CONT_ASSIGN49711100.00
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CONT_ASSIGN50211100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50411100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN51611100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN52711100.00
CONT_ASSIGN54311100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN56011100.00
CONT_ASSIGN56511100.00
CONT_ASSIGN56611100.00
CONT_ASSIGN57011100.00
CONT_ASSIGN58111100.00
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CONT_ASSIGN59411100.00
CONT_ASSIGN60211100.00
CONT_ASSIGN60311100.00
CONT_ASSIGN61211100.00
CONT_ASSIGN61311100.00
CONT_ASSIGN61511100.00
CONT_ASSIGN62111100.00
CONT_ASSIGN62211100.00
CONT_ASSIGN62911100.00
CONT_ASSIGN63011100.00
CONT_ASSIGN63711100.00
CONT_ASSIGN63811100.00
CONT_ASSIGN64911100.00
CONT_ASSIGN65011100.00
CONT_ASSIGN66011100.00
CONT_ASSIGN66111100.00
CONT_ASSIGN69011100.00
CONT_ASSIGN69211100.00
CONT_ASSIGN69611100.00
CONT_ASSIGN70011100.00
CONT_ASSIGN70211100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN73311100.00
CONT_ASSIGN73511100.00
CONT_ASSIGN73911100.00
CONT_ASSIGN74311100.00
CONT_ASSIGN74511100.00
CONT_ASSIGN74711100.00
CONT_ASSIGN80711100.00
CONT_ASSIGN81111100.00
CONT_ASSIGN81411100.00
CONT_ASSIGN82411100.00
CONT_ASSIGN82911100.00
CONT_ASSIGN83511100.00
CONT_ASSIGN83611100.00
CONT_ASSIGN83711100.00
CONT_ASSIGN83811100.00
CONT_ASSIGN84111100.00
CONT_ASSIGN87711100.00
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CONT_ASSIGN87711100.00
CONT_ASSIGN87711100.00
CONT_ASSIGN87711100.00
CONT_ASSIGN87711100.00
CONT_ASSIGN90111100.00
CONT_ASSIGN90211100.00
CONT_ASSIGN90511100.00
CONT_ASSIGN90611100.00
CONT_ASSIGN90711100.00
CONT_ASSIGN90811100.00
CONT_ASSIGN91011100.00
CONT_ASSIGN92511100.00
CONT_ASSIGN92711100.00
CONT_ASSIGN92911100.00
CONT_ASSIGN93511100.00
CONT_ASSIGN93811100.00
CONT_ASSIGN93911100.00
CONT_ASSIGN96311100.00
CONT_ASSIGN96311100.00
CONT_ASSIGN96311100.00
CONT_ASSIGN96311100.00
CONT_ASSIGN96311100.00
CONT_ASSIGN96311100.00
CONT_ASSIGN96311100.00
CONT_ASSIGN96411100.00
CONT_ASSIGN96411100.00
CONT_ASSIGN96411100.00
CONT_ASSIGN96411100.00
CONT_ASSIGN96411100.00
CONT_ASSIGN96411100.00
CONT_ASSIGN96411100.00
CONT_ASSIGN96711100.00
CONT_ASSIGN96711100.00
CONT_ASSIGN96711100.00
CONT_ASSIGN96711100.00
CONT_ASSIGN96711100.00
CONT_ASSIGN96711100.00
CONT_ASSIGN96711100.00
CONT_ASSIGN97011100.00
CONT_ASSIGN97011100.00
CONT_ASSIGN97011100.00
CONT_ASSIGN97011100.00
CONT_ASSIGN97011100.00
CONT_ASSIGN97011100.00
CONT_ASSIGN97011100.00
CONT_ASSIGN97311100.00
CONT_ASSIGN97311100.00
CONT_ASSIGN97311100.00
CONT_ASSIGN97311100.00
CONT_ASSIGN97311100.00
CONT_ASSIGN97311100.00
CONT_ASSIGN97311100.00
CONT_ASSIGN97411100.00
CONT_ASSIGN97411100.00
CONT_ASSIGN97411100.00
CONT_ASSIGN97411100.00
CONT_ASSIGN97411100.00
CONT_ASSIGN97411100.00
CONT_ASSIGN97411100.00
CONT_ASSIGN99411100.00
CONT_ASSIGN101211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
223 1 1
224 1 1
225 1 1
226 1 1
227 1 1
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 1 1
235 1 1
236 1 1
237 1 1
238 1 1
239 1 1
240 1 1
241 1 1
242 1 1
244 1 1
245 1 1
246 1 1
247 1 1
248 1 1
249 1 1
250 1 1
251 1 1
252 1 1
253 1 1
254 1 1
255 1 1
256 1 1
257 1 1
258 1 1
259 1 1
260 1 1
261 1 1
262 1 1
263 1 1
302 1 1
307 1 1
314 1 1
320 1 1
322 1 1
324 1 1
326 1 1
328 1 1
331 1 1
335 1 1
339 1 1
347 1 1
350 1 1
353 1 1
356 1 1
359 1 1
361 1 1
362 1 1
367 1 1
370 1 1
373 1 1
378 31 31
382 1 1
384 1 1
385 1 1
388 1 1
407 1 1
410 1 1
414 1 1
423 1 1
424 1 1
425 1 1
426 1 1
429 19 19
444 1 1
445 1 1
446 1 1
447 1 1
450 3 3
464 1 1
471 1 1
472 1 1
473 1 1
474 1 1
475 1 1
490 1 1
491 1 1
493 1 1
494 1 1
496 1 1
497 1 1
499 1 1
500 1 1
502 1 1
503 1 1
504 1 1
507 1 1
516 1 1
523 1 1
527 1 1
543 1 1
550 1 1
558 1 1
560 1 1
565 1 1
566 1 1
570 1 1
581 1 1
582 1 1
593 1 1
594 1 1
602 1 1
603 1 1
612 1 1
613 1 1
615 1 1
621 1 1
622 1 1
629 1 1
630 1 1
637 1 1
638 1 1
649 1 1
650 1 1
660 1 1
661 1 1
690 1 1
692 1 1
696 1 1
700 1 1
702 1 1
704 1 1
733 1 1
735 1 1
739 1 1
743 1 1
745 1 1
747 1 1
807 1 1
811 1 1
814 1 1
824 1 1
829 1 1
835 1 1
836 1 1
837 1 1
838 1 1
841 1 1
877 7 7
901 1 1
902 1 1
905 1 1
906 1 1
907 1 1
908 1 1
910 1 1
925 1 1
927 1 1
929 1 1
935 1 1
938 1 1
939 1 1
963 7 7
964 7 7
967 7 7
970 7 7
973 7 7
974 7 7
994 1 1
1012 1 1


Cond Coverage for Module : edn_core
TotalCoveredPercent
Conditions68061991.03
Logical68061991.03
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
302-69091.38
690-101290.38

Branch Coverage for Module : edn_core
Line No.TotalCoveredPercent
Branches 113 111 98.23
TERNARY 507 6 6 100.00
TERNARY 516 4 4 100.00
TERNARY 527 7 7 100.00
TERNARY 543 2 2 100.00
TERNARY 550 5 5 100.00
TERNARY 570 7 6 85.71
TERNARY 582 7 6 85.71
TERNARY 594 3 3 100.00
TERNARY 603 4 4 100.00
TERNARY 622 3 3 100.00
TERNARY 630 3 3 100.00
TERNARY 638 5 5 100.00
TERNARY 650 5 5 100.00
TERNARY 661 4 4 100.00
TERNARY 692 2 2 100.00
TERNARY 696 2 2 100.00
TERNARY 735 2 2 100.00
TERNARY 739 2 2 100.00
TERNARY 814 6 6 100.00
TERNARY 829 3 3 100.00
TERNARY 910 3 3 100.00
TERNARY 927 2 2 100.00
TERNARY 929 3 3 100.00
TERNARY 967 3 3 100.00
TERNARY 967 3 3 100.00
TERNARY 967 3 3 100.00
TERNARY 967 3 3 100.00
TERNARY 967 3 3 100.00
TERNARY 967 3 3 100.00
TERNARY 967 3 3 100.00
IF 223 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 507 ((!edn_enable_fo[CsrngCmdReq])) ? -2-: 507 (boot_wr_ins_cmd) ? -3-: 507 (boot_wr_gen_cmd) ? -4-: 507 (boot_wr_uni_cmd) ? -5-: 507 (sw_cmd_req_load) ?

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T18,T24,T25
0 0 1 - - Covered T18,T25,T75
0 0 0 1 - Covered T75,T14,T30
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 516 ((!edn_enable_fo[CsrngCmdReqValid])) ? -2-: 516 (cs_cmd_handshake) ? -3-: 516 ((((sw_cmd_req_load || boot_wr_ins_cmd) || boot_wr_gen_cmd) || boot_wr_uni_cmd)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 527 ((!edn_enable_fo[CsrngCmdReqOut])) ? -2-: 527 ((send_rescmd || capt_rescmd_fifo_cnt)) ? -3-: 527 (sfifo_rescmd_pop) ? -4-: 527 ((send_gencmd || capt_gencmd_fifo_cnt)) ? -5-: 527 (sfifo_gencmd_pop) ? -6-: 527 ((cs_cmd_req_vld_q && (!cs_cmd_handshake))) ?

Branches:
-1--2--3--4--5--6-StatusTests
1 - - - - - Covered T1,T2,T3
0 1 1 - - - Covered T1,T10,T14
0 1 0 - - - Covered T1,T10,T21
0 0 - 1 1 - Covered T1,T10,T14
0 0 - 1 0 - Covered T1,T10,T14
0 0 - 0 - 1 Covered T1,T2,T3
0 0 - 0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 543 ((!edn_enable_fo[CsrngCmdReqValidOut])) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 550 ((!edn_enable_fo[CsrngCmdReqValidOut])) ? -2-: 550 (cmd_sent) ? -3-: 550 ((send_rescmd || capt_rescmd_fifo_cnt)) ? -4-: 550 ((send_gencmd || capt_gencmd_fifo_cnt)) ?

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T10,T14
0 0 1 - Covered T1,T10,T14
0 0 0 1 Covered T1,T10,T14
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 570 ((!edn_enable_fo[SwCmdSts])) ? -2-: 570 ((!sw_cmd_mode)) ? -3-: 570 (reject_csrng_entropy) ? -4-: 570 (sw_cmd_req_load) ? -5-: 570 (accept_sw_cmds_pulse) ? -6-: 570 (csrng_cmd_i.csrng_rsp_ack) ?

Branches:
-1--2--3--4--5--6-StatusTests
1 - - - - - Covered T1,T2,T3
0 1 - - - - Covered T1,T18,T9
0 0 1 - - - Not Covered
0 0 0 1 - - Covered T1,T2,T3
0 0 0 0 1 - Covered T1,T2,T3
0 0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 582 ((!edn_enable_fo[SwCmdSts])) ? -2-: 582 ((!sw_cmd_mode)) ? -3-: 582 (reject_csrng_entropy) ? -4-: 582 (sw_cmd_req_load) ? -5-: 582 (accept_sw_cmds_pulse) ? -6-: 582 (cs_cmd_handshake) ?

Branches:
-1--2--3--4--5--6-StatusTests
1 - - - - - Covered T1,T2,T3
0 1 - - - - Covered T1,T18,T9
0 0 1 - - - Not Covered
0 0 0 1 - - Covered T1,T2,T3
0 0 0 0 1 - Covered T1,T2,T3
0 0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 594 ((!edn_enable_fo[SwCmdSts])) ? -2-: 594 (((csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode) && (!reject_csrng_entropy))) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 603 ((!edn_enable_fo[SwCmdSts])) ? -2-: 603 (sw_cmd_req_load) ? -3-: 603 (((csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode) && (!reject_csrng_entropy))) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 622 ((main_sm_done_pulse || main_sm_idle)) ? -2-: 622 ((boot_send_ins_cmd && cs_hw_cmd_handshake)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T18,T24,T25
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 630 ((main_sm_done_pulse || main_sm_idle)) ? -2-: 630 ((auto_req_mode_busy && cs_hw_cmd_handshake)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T10,T14
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 638 ((!edn_enable_fo[HwCmdSts])) ? -2-: 638 (((csrng_cmd_i.csrng_rsp_ack && (!sw_cmd_mode)) && (!reject_csrng_entropy))) ? -3-: 638 (reject_csrng_entropy) ? -4-: 638 (cs_hw_cmd_handshake) ?

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T18,T10
0 0 1 - Covered T18,T9,T24
0 0 0 1 Covered T1,T18,T10
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 650 ((!edn_enable_fo[HwCmdSts])) ? -2-: 650 (((csrng_cmd_i.csrng_rsp_ack && (!sw_cmd_mode)) && (!reject_csrng_entropy))) ? -3-: 650 (reject_csrng_entropy) ? -4-: 650 (cs_hw_cmd_handshake) ?

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T18,T10
0 0 1 - Covered T18,T9,T24
0 0 0 1 Covered T1,T18,T10
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 661 ((!edn_enable_fo[HwCmdSts])) ? -2-: 661 (reject_csrng_entropy) ? -3-: 661 (cs_hw_cmd_handshake_1st) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T18,T9,T24
0 0 1 Covered T1,T18,T10
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 692 (rescmd_handshake) ?

Branches:
-1-StatusTests
1 Covered T1,T10,T21
0 Covered T1,T2,T3


LineNo. Expression -1-: 696 (auto_req_mode_busy) ?

Branches:
-1-StatusTests
1 Covered T1,T10,T14
0 Covered T1,T2,T3


LineNo. Expression -1-: 735 (gencmd_handshake) ?

Branches:
-1-StatusTests
1 Covered T1,T10,T14
0 Covered T1,T2,T3


LineNo. Expression -1-: 739 (auto_req_mode_busy) ?

Branches:
-1-StatusTests
1 Covered T1,T10,T14
0 Covered T1,T2,T3


LineNo. Expression -1-: 814 ((!edn_enable_fo[CmdFifoCnt])) ? -2-: 814 ((cmd_fifo_rst_fo[3] || main_sm_done_pulse)) ? -3-: 814 (capt_gencmd_fifo_cnt) ? -4-: 814 (capt_rescmd_fifo_cnt) ? -5-: 814 ((sfifo_gencmd_pop || sfifo_rescmd_pop)) ?

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T1,T2,T3
0 0 1 - - Covered T1,T10,T14
0 0 0 1 - Covered T1,T10,T14
0 0 0 0 1 Covered T1,T10,T21
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 829 ((capt_gencmd_fifo_cnt || capt_rescmd_fifo_cnt)) ? -2-: 829 (cs_hw_cmd_handshake) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T10,T14
0 1 Covered T1,T18,T9
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 910 ((!edn_enable_fo[CsrngFipsEn])) ? -2-: 910 ((packer_cs_push && packer_cs_wready)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 927 (cs_rdata_capt_vld) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 929 ((!edn_enable_fo[CsrngDataVld])) ? -2-: 929 (cs_rdata_capt_vld) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 967 (packer_ep_clr[0]) ? -2-: 967 ((packer_ep_push[0] && packer_ep_wready[0])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T9
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 967 (packer_ep_clr[1]) ? -2-: 967 ((packer_ep_push[1] && packer_ep_wready[1])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T3,T30
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 967 (packer_ep_clr[2]) ? -2-: 967 ((packer_ep_push[2] && packer_ep_wready[2])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T3,T18
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 967 (packer_ep_clr[3]) ? -2-: 967 ((packer_ep_push[3] && packer_ep_wready[3])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T3,T11
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 967 (packer_ep_clr[4]) ? -2-: 967 ((packer_ep_push[4] && packer_ep_wready[4])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T21,T22
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 967 (packer_ep_clr[5]) ? -2-: 967 ((packer_ep_push[5] && packer_ep_wready[5])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T39,T40
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 967 (packer_ep_clr[6]) ? -2-: 967 ((packer_ep_push[6] && packer_ep_wready[6])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T3,T14,T22
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 223 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : edn_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CsErrAcceptNoEntropy_A 223367997 35041 0 0
CsErrIssueNoCommands_A 223367997 35041 0 0


CsErrAcceptNoEntropy_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 223367997 35041 0 0
T9 2113 203 0 0
T10 1480 0 0 0
T14 0 197 0 0
T18 2169 136 0 0
T23 1464 0 0 0
T24 1516 136 0 0
T25 2358 207 0 0
T26 2149 242 0 0
T47 957 0 0 0
T75 2299 148 0 0
T76 3226 0 0 0
T81 0 136 0 0
T85 0 148 0 0
T105 0 136 0 0

CsErrIssueNoCommands_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 223367997 35041 0 0
T9 2113 203 0 0
T10 1480 0 0 0
T14 0 197 0 0
T18 2169 136 0 0
T23 1464 0 0 0
T24 1516 136 0 0
T25 2358 207 0 0
T26 2149 242 0 0
T47 957 0 0 0
T75 2299 148 0 0
T76 3226 0 0 0
T81 0 136 0 0
T85 0 148 0 0
T105 0 136 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%