Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T9,T24

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T6,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T46,T83,T193
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T84,T67,T122
DataWait->Error	99	Covered	T6,T194,T195
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T40,T72,T93
EndPointClear->Error	99	Covered	T16,T19,T196
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T2,T18,T9
Idle->Error	99	Covered	T4,T6,T7

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T4,T6,T7
default	-	-	-	-	Covered	T4,T7,T78

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T7
0	1	Covered	T18,T9,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1563575979	1052470	0	0
FpvSecCmErrorStEscalate_A	1563575979	1060660	0	0
u_state_regs_A	1563537038	1562210244	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1563575979	1052470	0	0
T4	14609	7762	0	0
T5	6556550	0	0	0
T6	0	1820	0	0
T7	0	4626	0	0
T11	12250	0	0	0
T14	13377	0	0	0
T15	0	1414	0	0
T16	0	54068	0	0
T21	7889	0	0	0
T22	17297	0	0	0
T30	33852	0	0	0
T46	6895	0	0	0
T68	0	7769	0	0
T77	17633	0	0	0
T78	0	4577	0	0
T79	0	2400	0	0
T80	0	6320	0	0
T81	13272	0	0	0
T100	0	2478	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1563575979	1060660	0	0
T4	14609	7769	0	0
T5	6556550	0	0	0
T6	0	1827	0	0
T7	0	4633	0	0
T11	12250	0	0	0
T14	13377	0	0	0
T15	0	1421	0	0
T16	0	54978	0	0
T21	7889	0	0	0
T22	17297	0	0	0
T30	33852	0	0	0
T46	6895	0	0	0
T68	0	7776	0	0
T77	17633	0	0	0
T78	0	4584	0	0
T79	0	2407	0	0
T80	0	6327	0	0
T81	13272	0	0	0
T100	0	2485	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1563537038	1562210244	0	0
T1	19663	19306	0	0
T2	1050917	1050861	0	0
T3	36008	35448	0	0
T9	14791	14371	0	0
T10	10360	9709	0	0
T18	15183	14511	0	0
T23	10248	9562	0	0
T24	10612	10262	0	0
T25	16506	15953	0	0
T26	15043	14364	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T9,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T3,T11
DataWait	75	Covered	T1,T3,T11
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T6,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T3,T11
DataWait->AckPls	80	Covered	T1,T3,T11
DataWait->Disabled	107	Covered	T197,T198,T150
DataWait->Error	99	Covered	T149,T199
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T40,T72,T93
EndPointClear->Error	99	Covered	T16,T19,T196
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T3,T11
Idle->Disabled	107	Covered	T2,T18,T9
Idle->Error	99	Covered	T4,T6,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T3,T11
Idle	-	1	0	-	Covered	T1,T3,T11
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T3,T11
DataWait	-	-	-	0	Covered	T1,T3,T11
AckPls	-	-	-	-	Covered	T1,T3,T11
Error	-	-	-	-	Covered	T4,T6,T7
default	-	-	-	-	Covered	T16,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T7
0	1	Covered	T18,T9,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	223367997	150710	0	0
FpvSecCmErrorStEscalate_A	223367997	151880	0	0
u_state_regs_A	223367997	223178455	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	150710	0	0
T4	2087	1116	0	0
T5	936650	0	0	0
T6	0	260	0	0
T7	0	668	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	202	0	0
T16	0	7724	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T46	985	0	0	0
T68	0	1117	0	0
T77	2519	0	0	0
T78	0	661	0	0
T79	0	350	0	0
T80	0	910	0	0
T81	1896	0	0	0
T100	0	354	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	151880	0	0
T4	2087	1117	0	0
T5	936650	0	0	0
T6	0	261	0	0
T7	0	669	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	203	0	0
T16	0	7854	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T46	985	0	0	0
T68	0	1118	0	0
T77	2519	0	0	0
T78	0	662	0	0
T79	0	351	0	0
T80	0	911	0	0
T81	1896	0	0	0
T100	0	355	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T9,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T21,T22
DataWait	75	Covered	T1,T21,T22
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T6,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T21,T22
DataWait->AckPls	80	Covered	T1,T21,T22
DataWait->Disabled	107	Covered	T169,T200,T201
DataWait->Error	99	Covered	T100,T191
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T40,T72,T93
EndPointClear->Error	99	Covered	T16,T19,T196
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T21,T22
Idle->Disabled	107	Covered	T2,T18,T9
Idle->Error	99	Covered	T4,T6,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T21,T22
Idle	-	1	0	-	Covered	T1,T21,T22
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T21,T22
DataWait	-	-	-	0	Covered	T1,T21,T22
AckPls	-	-	-	-	Covered	T1,T21,T22
Error	-	-	-	-	Covered	T4,T6,T7
default	-	-	-	-	Covered	T16,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T7
0	1	Covered	T18,T9,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	223367997	150710	0	0
FpvSecCmErrorStEscalate_A	223367997	151880	0	0
u_state_regs_A	223367997	223178455	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	150710	0	0
T4	2087	1116	0	0
T5	936650	0	0	0
T6	0	260	0	0
T7	0	668	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	202	0	0
T16	0	7724	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T46	985	0	0	0
T68	0	1117	0	0
T77	2519	0	0	0
T78	0	661	0	0
T79	0	350	0	0
T80	0	910	0	0
T81	1896	0	0	0
T100	0	354	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	151880	0	0
T4	2087	1117	0	0
T5	936650	0	0	0
T6	0	261	0	0
T7	0	669	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	203	0	0
T16	0	7854	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T46	985	0	0	0
T68	0	1118	0	0
T77	2519	0	0	0
T78	0	662	0	0
T79	0	351	0	0
T80	0	911	0	0
T81	1896	0	0	0
T100	0	355	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T9,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T39,T40
DataWait	75	Covered	T1,T39,T40
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T6,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T39,T40
DataWait->AckPls	80	Covered	T1,T39,T40
DataWait->Disabled	107	Covered	T67,T123,T202
DataWait->Error	99	Covered	T15
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T40,T72,T93
EndPointClear->Error	99	Covered	T16,T19,T196
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T39,T40
Idle->Disabled	107	Covered	T2,T18,T9
Idle->Error	99	Covered	T4,T6,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T39,T40
Idle	-	1	0	-	Covered	T1,T39,T40
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T39,T40
DataWait	-	-	-	0	Covered	T1,T39,T40
AckPls	-	-	-	-	Covered	T1,T39,T40
Error	-	-	-	-	Covered	T4,T6,T7
default	-	-	-	-	Covered	T16,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T7
0	1	Covered	T18,T9,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	223367997	150710	0	0
FpvSecCmErrorStEscalate_A	223367997	151880	0	0
u_state_regs_A	223367997	223178455	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	150710	0	0
T4	2087	1116	0	0
T5	936650	0	0	0
T6	0	260	0	0
T7	0	668	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	202	0	0
T16	0	7724	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T46	985	0	0	0
T68	0	1117	0	0
T77	2519	0	0	0
T78	0	661	0	0
T79	0	350	0	0
T80	0	910	0	0
T81	1896	0	0	0
T100	0	354	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	151880	0	0
T4	2087	1117	0	0
T5	936650	0	0	0
T6	0	261	0	0
T7	0	669	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	203	0	0
T16	0	7854	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T46	985	0	0	0
T68	0	1118	0	0
T77	2519	0	0	0
T78	0	662	0	0
T79	0	351	0	0
T80	0	911	0	0
T81	1896	0	0	0
T100	0	355	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T9,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T9
DataWait	75	Covered	T1,T2,T9
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T6,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T203
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T9
DataWait->AckPls	80	Covered	T1,T2,T9
DataWait->Disabled	107	Covered	T204,T205
DataWait->Error	99	Covered	T6,T194,T195
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T40,T72,T93
EndPointClear->Error	99	Covered	T16,T19,T196
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T9
Idle->Disabled	107	Covered	T2,T18,T9
Idle->Error	99	Covered	T15,T100,T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T9
Idle	-	1	0	-	Covered	T1,T2,T9
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T9
DataWait	-	-	-	0	Covered	T1,T2,T9
AckPls	-	-	-	-	Covered	T1,T2,T9
Error	-	-	-	-	Covered	T4,T6,T7
default	-	-	-	-	Covered	T4,T7,T78

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T7
0	1	Covered	T18,T9,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	223367997	148210	0	0
FpvSecCmErrorStEscalate_A	223367997	149380	0	0
u_state_regs_A	223329056	223139514	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	148210	0	0
T4	2087	1066	0	0
T5	936650	0	0	0
T6	0	260	0	0
T7	0	618	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	202	0	0
T16	0	7724	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T46	985	0	0	0
T68	0	1067	0	0
T77	2519	0	0	0
T78	0	611	0	0
T79	0	300	0	0
T80	0	860	0	0
T81	1896	0	0	0
T100	0	354	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	149380	0	0
T4	2087	1067	0	0
T5	936650	0	0	0
T6	0	261	0	0
T7	0	619	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	203	0	0
T16	0	7854	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T46	985	0	0	0
T68	0	1068	0	0
T77	2519	0	0	0
T78	0	612	0	0
T79	0	301	0	0
T80	0	861	0	0
T81	1896	0	0	0
T100	0	355	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223329056	223139514	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T9,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T3,T30
DataWait	75	Covered	T1,T3,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T6,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T83
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T3,T30
DataWait->AckPls	80	Covered	T1,T3,T30
DataWait->Disabled	107	Covered	T206,T207
DataWait->Error	99	Covered	T208,T192,T115
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T40,T72,T93
EndPointClear->Error	99	Covered	T16,T19,T196
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T3,T30
Idle->Disabled	107	Covered	T2,T18,T9
Idle->Error	99	Covered	T4,T6,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T3,T30
Idle	-	1	0	-	Covered	T1,T3,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T3,T30
DataWait	-	-	-	0	Covered	T1,T3,T30
AckPls	-	-	-	-	Covered	T1,T3,T30
Error	-	-	-	-	Covered	T4,T6,T7
default	-	-	-	-	Covered	T16,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T7
0	1	Covered	T18,T9,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	223367997	150710	0	0
FpvSecCmErrorStEscalate_A	223367997	151880	0	0
u_state_regs_A	223367997	223178455	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	150710	0	0
T4	2087	1116	0	0
T5	936650	0	0	0
T6	0	260	0	0
T7	0	668	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	202	0	0
T16	0	7724	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T46	985	0	0	0
T68	0	1117	0	0
T77	2519	0	0	0
T78	0	661	0	0
T79	0	350	0	0
T80	0	910	0	0
T81	1896	0	0	0
T100	0	354	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	151880	0	0
T4	2087	1117	0	0
T5	936650	0	0	0
T6	0	261	0	0
T7	0	669	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	203	0	0
T16	0	7854	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T46	985	0	0	0
T68	0	1118	0	0
T77	2519	0	0	0
T78	0	662	0	0
T79	0	351	0	0
T80	0	911	0	0
T81	1896	0	0	0
T100	0	355	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T9,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T3,T18
DataWait	75	Covered	T1,T3,T18
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T6,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T209
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T3,T18
DataWait->AckPls	80	Covered	T1,T3,T18
DataWait->Disabled	107	Covered	T84,T122,T210
DataWait->Error	99	Covered	T50,T211,T188
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T40,T72,T93
EndPointClear->Error	99	Covered	T16,T19,T196
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T3,T18
Idle->Disabled	107	Covered	T2,T18,T9
Idle->Error	99	Covered	T4,T6,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T3,T18
Idle	-	1	0	-	Covered	T1,T3,T18
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T3,T18
DataWait	-	-	-	0	Covered	T1,T3,T18
AckPls	-	-	-	-	Covered	T1,T3,T18
Error	-	-	-	-	Covered	T4,T6,T7
default	-	-	-	-	Covered	T16,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T7
0	1	Covered	T18,T9,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	223367997	150710	0	0
FpvSecCmErrorStEscalate_A	223367997	151880	0	0
u_state_regs_A	223367997	223178455	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	150710	0	0
T4	2087	1116	0	0
T5	936650	0	0	0
T6	0	260	0	0
T7	0	668	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	202	0	0
T16	0	7724	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T46	985	0	0	0
T68	0	1117	0	0
T77	2519	0	0	0
T78	0	661	0	0
T79	0	350	0	0
T80	0	910	0	0
T81	1896	0	0	0
T100	0	354	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	151880	0	0
T4	2087	1117	0	0
T5	936650	0	0	0
T6	0	261	0	0
T7	0	669	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	203	0	0
T16	0	7854	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T46	985	0	0	0
T68	0	1118	0	0
T77	2519	0	0	0
T78	0	662	0	0
T79	0	351	0	0
T80	0	911	0	0
T81	1896	0	0	0
T100	0	355	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T9,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T14,T22
DataWait	75	Covered	T3,T14,T22
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T6,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T46,T193,T212
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T14,T22
DataWait->AckPls	80	Covered	T3,T14,T22
DataWait->Disabled	107	Covered	T22
DataWait->Error	99	Covered	T17,T54,T116
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T19,T20
EndPointClear->Disabled	107	Covered	T40,T72,T93
EndPointClear->Error	99	Covered	T16,T19,T196
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T14,T22
Idle->Disabled	107	Covered	T2,T18,T9
Idle->Error	99	Covered	T4,T6,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T14,T22
Idle	-	1	0	-	Covered	T3,T14,T22
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T14,T22
DataWait	-	-	-	0	Covered	T3,T14,T22
AckPls	-	-	-	-	Covered	T3,T14,T22
Error	-	-	-	-	Covered	T4,T6,T7
default	-	-	-	-	Covered	T16,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T7
0	1	Covered	T18,T9,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	223367997	150710	0	0
FpvSecCmErrorStEscalate_A	223367997	151880	0	0
u_state_regs_A	223367997	223178455	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	150710	0	0
T4	2087	1116	0	0
T5	936650	0	0	0
T6	0	260	0	0
T7	0	668	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	202	0	0
T16	0	7724	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T46	985	0	0	0
T68	0	1117	0	0
T77	2519	0	0	0
T78	0	661	0	0
T79	0	350	0	0
T80	0	910	0	0
T81	1896	0	0	0
T100	0	354	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	151880	0	0
T4	2087	1117	0	0
T5	936650	0	0	0
T6	0	261	0	0
T7	0	669	0	0
T11	1750	0	0	0
T14	1911	0	0	0
T15	0	203	0	0
T16	0	7854	0	0
T21	1127	0	0	0
T22	2471	0	0	0
T30	4836	0	0	0
T46	985	0	0	0
T68	0	1118	0	0
T77	2519	0	0	0
T78	0	662	0	0
T79	0	351	0	0
T80	0	911	0	0
T81	1896	0	0	0
T100	0	355	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0