Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T18,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T35,T36,T94
1	1	0	Not Covered
1	1	1	Covered	T1,T18,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T32,T34,T37
1	0	1	Covered	T1,T18,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T10,T14

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	445990572	2373536	0	0
DepthKnown_A	446735994	446356910	0	0
RvalidKnown_A	446735994	446356910	0	0
WreadyKnown_A	446735994	446356910	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	446349260	2465811	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445990572	2373536	0	0
T1	5618	2565	0	0
T2	300262	0	0	0
T3	10288	0	0	0
T9	4226	510	0	0
T10	2960	1127	0	0
T14	0	562	0	0
T18	4338	289	0	0
T21	0	417	0	0
T22	0	2796	0	0
T23	2928	0	0	0
T24	3032	0	0	0
T25	4716	283	0	0
T26	4298	388	0	0
T75	0	319	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446735994	446356910	0	0
T1	5618	5516	0	0
T2	300262	300246	0	0
T3	10288	10128	0	0
T9	4226	4106	0	0
T10	2960	2774	0	0
T18	4338	4146	0	0
T23	2928	2732	0	0
T24	3032	2932	0	0
T25	4716	4558	0	0
T26	4298	4104	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446735994	446356910	0	0
T1	5618	5516	0	0
T2	300262	300246	0	0
T3	10288	10128	0	0
T9	4226	4106	0	0
T10	2960	2774	0	0
T18	4338	4146	0	0
T23	2928	2732	0	0
T24	3032	2932	0	0
T25	4716	4558	0	0
T26	4298	4104	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446735994	446356910	0	0
T1	5618	5516	0	0
T2	300262	300246	0	0
T3	10288	10128	0	0
T9	4226	4106	0	0
T10	2960	2774	0	0
T18	4338	4146	0	0
T23	2928	2732	0	0
T24	3032	2932	0	0
T25	4716	4558	0	0
T26	4298	4104	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	446349260	2465811	0	0
T1	5618	2565	0	0
T2	300262	0	0	0
T3	10288	0	0	0
T4	0	303	0	0
T9	4226	510	0	0
T10	2960	1127	0	0
T14	0	562	0	0
T18	4338	289	0	0
T21	0	417	0	0
T23	2928	0	0	0
T24	3032	0	0	0
T25	4716	283	0	0
T26	4298	388	0	0
T75	0	319	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T39,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T18,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T35,T94
1	1	0	Not Covered
1	1	1	Covered	T1,T18,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T32,T95,T96
1	0	1	Covered	T1,T18,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T10,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	222995286	1179723	0	0
DepthKnown_A	223367997	223178455	0	0
RvalidKnown_A	223367997	223178455	0	0
WreadyKnown_A	223367997	223178455	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	223174630	1225695	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222995286	1179723	0	0
T1	2809	1242	0	0
T2	150131	0	0	0
T3	5144	0	0	0
T9	2113	261	0	0
T10	1480	555	0	0
T14	0	287	0	0
T18	2169	143	0	0
T21	0	206	0	0
T22	0	1291	0	0
T23	1464	0	0	0
T24	1516	0	0	0
T25	2358	81	0	0
T26	2149	198	0	0
T75	0	157	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	223174630	1225695	0	0
T1	2809	1242	0	0
T2	150131	0	0	0
T3	5144	0	0	0
T4	0	156	0	0
T9	2113	261	0	0
T10	1480	555	0	0
T14	0	287	0	0
T18	2169	143	0	0
T21	0	206	0	0
T23	1464	0	0	0
T24	1516	0	0	0
T25	2358	81	0	0
T26	2149	198	0	0
T75	0	157	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T18,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T36,T97,T98
1	1	0	Not Covered
1	1	1	Covered	T1,T18,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T37,T99
1	0	1	Covered	T1,T18,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T10,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	222995286	1193813	0	0
DepthKnown_A	223367997	223178455	0	0
RvalidKnown_A	223367997	223178455	0	0
WreadyKnown_A	223367997	223178455	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	223174630	1240116	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222995286	1193813	0	0
T1	2809	1323	0	0
T2	150131	0	0	0
T3	5144	0	0	0
T9	2113	249	0	0
T10	1480	572	0	0
T14	0	275	0	0
T18	2169	146	0	0
T21	0	211	0	0
T22	0	1505	0	0
T23	1464	0	0	0
T24	1516	0	0	0
T25	2358	202	0	0
T26	2149	190	0	0
T75	0	162	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223367997	223178455	0	0
T1	2809	2758	0	0
T2	150131	150123	0	0
T3	5144	5064	0	0
T9	2113	2053	0	0
T10	1480	1387	0	0
T18	2169	2073	0	0
T23	1464	1366	0	0
T24	1516	1466	0	0
T25	2358	2279	0	0
T26	2149	2052	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	223174630	1240116	0	0
T1	2809	1323	0	0
T2	150131	0	0	0
T3	5144	0	0	0
T4	0	147	0	0
T9	2113	249	0	0
T10	1480	572	0	0
T14	0	275	0	0
T18	2169	146	0	0
T21	0	211	0	0
T23	1464	0	0	0
T24	1516	0	0	0
T25	2358	202	0	0
T26	2149	190	0	0
T75	0	162	0	0