Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.11	98.25	93.91	97.07	91.28	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.07	99.92	92.66	82.84	91.28	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T27,T16

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T17,T18
1	0	Covered	T4,T14,T35

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T41,T42,T43	Yes	T41,T42,T43	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T2,T3,T25	Yes	T2,T3,T25	INPUT
edn_i[1].edn_req	Yes	Yes	T25,T9,T19	Yes	T25,T9,T19	INPUT
edn_i[2].edn_req	Yes	Yes	T25,T27,T9	Yes	T25,T27,T9	INPUT
edn_i[3].edn_req	Yes	Yes	T25,T9,T28	Yes	T25,T9,T28	INPUT
edn_i[4].edn_req	Yes	Yes	T25,T9,T28	Yes	T25,T9,T28	INPUT
edn_i[5].edn_req	Yes	Yes	T25,T27,T9	Yes	T25,T27,T9	INPUT
edn_i[6].edn_req	Yes	Yes	T1,T4,T25	Yes	T1,T4,T25	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T3,T25	Yes	T2,T3,T25	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T25,T5	Yes	T3,T25,T5	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T2,T3,T25	Yes	T2,T3,T25	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T25,T9,T19	Yes	T25,T9,T19	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T9,T19,T44	Yes	T25,T9,T19	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T25,T9,T19	Yes	T25,T9,T19	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T25,T27,T9	Yes	T25,T27,T9	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T25,T9,T45	Yes	T25,T9,T20	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T25,T27,T9	Yes	T25,T27,T9	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T9,T46,T45	Yes	T25,T9,T46	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T46,T45,T11	Yes	T28,T46,T45	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T25,T9,T28	Yes	T25,T9,T28	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T25,T9,T28	Yes	T25,T9,T28	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T9,T28,T46	Yes	T9,T28,T46	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T25,T9,T28	Yes	T25,T9,T28	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T25,T27,T9	Yes	T25,T27,T9	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T25,T27,T46	Yes	T25,T27,T9	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T25,T27,T9	Yes	T25,T27,T9	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T1,T25,T28	Yes	T1,T25,T9	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T1,T28,T45	Yes	T1,T25,T9	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T1,T25,T9	Yes	T1,T25,T9	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T3,T25	Yes	T2,T3,T25	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T25,T5	Yes	T3,T25,T5	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T10,T47,T48	Yes	T10,T47,T48	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T27,T16	Yes	T1,T27,T16	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T14,T35	Yes	T4,T14,T35	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T27,T16	Yes	T1,T27,T16	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T14,T35	Yes	T4,T14,T35	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T2,T5,T26	Yes	T2,T5,T26	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T2,T5,T26	Yes	T2,T5,T26	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	196539342	196351457	0	0
CsrngAppIfOut_A	196539342	196351457	0	0
FpvSecCmCntAlertCheck_A	196539342	120	0	0
FpvSecCmGenCmdFifoRptrCheck_A	196539342	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	196539342	80	0	0
FpvSecCmMainFsmCheck_A	196539342	80	0	0
FpvSecCmRegWeOnehotCheck_A	196539342	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	196539342	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	196539342	80	0	0
IntrEdnCmdReqDoneKnownO_A	196539342	196351457	0	0
TlAReadyKnownO_A	196539342	196351457	0	0
TlDValidKnownO_A	196539342	196351457	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	196539342	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	196539342	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	196539342	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	196539342	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	196539342	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	196539342	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	196539342	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	196539342	612813	0	326
gen_edn_if_asserts[0].EdnDataStable_A	196539342	21395	0	432
gen_edn_if_asserts[0].EdnEndPointOut_A	196539342	196351457	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	196539342	162638	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	196539342	612813	0	326
gen_edn_if_asserts[1].EdnDataStable_A	196539342	3722	0	131
gen_edn_if_asserts[1].EdnEndPointOut_A	196539342	196351457	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	196539342	162638	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	196539342	612813	0	326
gen_edn_if_asserts[2].EdnDataStable_A	196539342	4405	0	127
gen_edn_if_asserts[2].EdnEndPointOut_A	196539342	196351457	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	196539342	162638	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	196539342	612813	0	326
gen_edn_if_asserts[3].EdnDataStable_A	196539342	2704	0	120
gen_edn_if_asserts[3].EdnEndPointOut_A	196539342	196351457	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	196539342	162638	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	196539342	612813	0	326
gen_edn_if_asserts[4].EdnDataStable_A	196539342	2125	0	92
gen_edn_if_asserts[4].EdnEndPointOut_A	196539342	196351457	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	196539342	162638	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	196539342	612813	0	326
gen_edn_if_asserts[5].EdnDataStable_A	196539342	3856	0	101
gen_edn_if_asserts[5].EdnEndPointOut_A	196539342	196351457	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	196539342	162638	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	196539342	612813	0	326
gen_edn_if_asserts[6].EdnDataStable_A	196539342	3221	0	92
gen_edn_if_asserts[6].EdnEndPointOut_A	196539342	196351457	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	196539342	162638	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	120	0	0
T8	0	1	0	0
T14	2133	1	0	0
T15	0	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T24	3192	0	0	0
T35	1832	0	0	0
T47	2054	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	4833	0	0	0
T55	2694	0	0	0
T56	1975	0	0	0
T57	2339	0	0	0
T58	2880	0	0	0
T59	4164	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	80	0	0
T8	2023	0	0	0
T11	2279	0	0	0
T15	24698	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T60	0	10	0	0
T61	0	20	0	0
T62	1279	0	0	0
T63	1457	0	0	0
T64	2141	0	0	0
T65	2797	0	0	0
T66	2981	0	0	0
T67	1234	0	0	0
T68	1251	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	80	0	0
T8	2023	0	0	0
T11	2279	0	0	0
T15	24698	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T60	0	10	0	0
T61	0	20	0	0
T62	1279	0	0	0
T63	1457	0	0	0
T64	2141	0	0	0
T65	2797	0	0	0
T66	2981	0	0	0
T67	1234	0	0	0
T68	1251	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	80	0	0
T8	2023	0	0	0
T11	2279	0	0	0
T15	24698	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T60	0	10	0	0
T61	0	20	0	0
T62	1279	0	0	0
T63	1457	0	0	0
T64	2141	0	0	0
T65	2797	0	0	0
T66	2981	0	0	0
T67	1234	0	0	0
T68	1251	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	80	0	0
T8	2023	0	0	0
T11	2279	0	0	0
T15	24698	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T60	0	10	0	0
T61	0	20	0	0
T62	1279	0	0	0
T63	1457	0	0	0
T64	2141	0	0	0
T65	2797	0	0	0
T66	2981	0	0	0
T67	1234	0	0	0
T68	1251	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	80	0	0
T8	2023	0	0	0
T11	2279	0	0	0
T15	24698	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T60	0	10	0	0
T61	0	20	0	0
T62	1279	0	0	0
T63	1457	0	0	0
T64	2141	0	0	0
T65	2797	0	0	0
T66	2981	0	0	0
T67	1234	0	0	0
T68	1251	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	80	0	0
T8	2023	0	0	0
T11	2279	0	0	0
T15	24698	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T60	0	10	0	0
T61	0	20	0	0
T62	1279	0	0	0
T63	1457	0	0	0
T64	2141	0	0	0
T65	2797	0	0	0
T66	2981	0	0	0
T67	1234	0	0	0
T68	1251	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	80	0	0
T8	2023	0	0	0
T11	2279	0	0	0
T15	24698	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T60	0	10	0	0
T61	0	20	0	0
T62	1279	0	0	0
T63	1457	0	0	0
T64	2141	0	0	0
T65	2797	0	0	0
T66	2981	0	0	0
T67	1234	0	0	0
T68	1251	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	80	0	0
T8	2023	0	0	0
T11	2279	0	0	0
T15	24698	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T60	0	10	0	0
T61	0	20	0	0
T62	1279	0	0	0
T63	1457	0	0	0
T64	2141	0	0	0
T65	2797	0	0	0
T66	2981	0	0	0
T67	1234	0	0	0
T68	1251	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	80	0	0
T8	2023	0	0	0
T11	2279	0	0	0
T15	24698	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T60	0	10	0	0
T61	0	20	0	0
T62	1279	0	0	0
T63	1457	0	0	0
T64	2141	0	0	0
T65	2797	0	0	0
T66	2981	0	0	0
T67	1234	0	0	0
T68	1251	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	80	0	0
T8	2023	0	0	0
T11	2279	0	0	0
T15	24698	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T60	0	10	0	0
T61	0	20	0	0
T62	1279	0	0	0
T63	1457	0	0	0
T64	2141	0	0	0
T65	2797	0	0	0
T66	2981	0	0	0
T67	1234	0	0	0
T68	1251	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	80	0	0
T8	2023	0	0	0
T11	2279	0	0	0
T15	24698	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T60	0	10	0	0
T61	0	20	0	0
T62	1279	0	0	0
T63	1457	0	0	0
T64	2141	0	0	0
T65	2797	0	0	0
T66	2981	0	0	0
T67	1234	0	0	0
T68	1251	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	80	0	0
T8	2023	0	0	0
T11	2279	0	0	0
T15	24698	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T60	0	10	0	0
T61	0	20	0	0
T62	1279	0	0	0
T63	1457	0	0	0
T64	2141	0	0	0
T65	2797	0	0	0
T66	2981	0	0	0
T67	1234	0	0	0
T68	1251	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	80	0	0
T8	2023	0	0	0
T11	2279	0	0	0
T15	24698	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T60	0	10	0	0
T61	0	20	0	0
T62	1279	0	0	0
T63	1457	0	0	0
T64	2141	0	0	0
T65	2797	0	0	0
T66	2981	0	0	0
T67	1234	0	0	0
T68	1251	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	612813	0	326
T1	1829	128	0	0
T2	10548	4261	0	2
T3	6281	57	0	0
T4	736	335	0	0
T5	26006	3738	0	2
T9	3037	73	0	0
T15	0	0	0	2
T20	0	0	0	2
T25	2222	11	0	0
T26	13021	821	0	0
T27	1874	128	0	0
T28	3882	29	0	0
T41	0	0	0	2
T42	0	0	0	2
T43	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	21395	0	432
T2	10548	7	0	0
T3	6281	839	0	1
T4	736	0	0	0
T5	26006	24	0	0
T9	3037	3	0	1
T10	0	8	0	1
T16	2074	0	0	0
T25	2222	58	0	1
T26	13021	6	0	1
T27	1874	0	0	0
T28	3882	38	0	1
T29	0	3	0	1
T45	0	0	0	1
T46	0	12	0	1
T54	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	162638	0	0
T4	736	381	0	0
T5	26006	0	0	0
T6	0	268	0	0
T7	0	612	0	0
T8	0	968	0	0
T9	3037	0	0	0
T14	0	1109	0	0
T15	0	9913	0	0
T16	2074	0	0	0
T17	0	20685	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1112	0	0
T67	0	612	0	0
T72	0	637	0	0
T73	1529	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	612813	0	326
T1	1829	128	0	0
T2	10548	4261	0	2
T3	6281	57	0	0
T4	736	335	0	0
T5	26006	3738	0	2
T9	3037	73	0	0
T15	0	0	0	2
T20	0	0	0	2
T25	2222	11	0	0
T26	13021	821	0	0
T27	1874	128	0	0
T28	3882	29	0	0
T41	0	0	0	2
T42	0	0	0	2
T43	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	3722	0	131
T5	26006	0	0	0
T9	3037	13	0	1
T10	2584	0	0	0
T16	2074	0	0	0
T19	0	73	0	1
T25	2222	3	0	1
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T44	0	20	0	1
T45	0	3	0	1
T46	0	3	0	1
T47	0	4	0	1
T54	0	38	0	1
T64	0	22	0	1
T73	1529	0	0	0
T74	0	4	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	162638	0	0
T4	736	381	0	0
T5	26006	0	0	0
T6	0	268	0	0
T7	0	612	0	0
T8	0	968	0	0
T9	3037	0	0	0
T14	0	1109	0	0
T15	0	9913	0	0
T16	2074	0	0	0
T17	0	20685	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1112	0	0
T67	0	612	0	0
T72	0	637	0	0
T73	1529	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	612813	0	326
T1	1829	128	0	0
T2	10548	4261	0	2
T3	6281	57	0	0
T4	736	335	0	0
T5	26006	3738	0	2
T9	3037	73	0	0
T15	0	0	0	2
T20	0	0	0	2
T25	2222	11	0	0
T26	13021	821	0	0
T27	1874	128	0	0
T28	3882	29	0	0
T41	0	0	0	2
T42	0	0	0	2
T43	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	4405	0	127
T5	26006	0	0	0
T9	3037	17	0	1
T10	2584	0	0	0
T16	2074	0	0	0
T20	0	4	0	0
T25	2222	32	0	1
T26	13021	0	0	0
T27	1874	4	0	1
T28	3882	3	0	1
T29	826	0	0	0
T45	0	17	0	1
T46	0	3	0	1
T54	0	3	0	1
T57	0	3	0	1
T58	0	4	0	1
T73	1529	0	0	0
T75	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	162638	0	0
T4	736	381	0	0
T5	26006	0	0	0
T6	0	268	0	0
T7	0	612	0	0
T8	0	968	0	0
T9	3037	0	0	0
T14	0	1109	0	0
T15	0	9913	0	0
T16	2074	0	0	0
T17	0	20685	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1112	0	0
T67	0	612	0	0
T72	0	637	0	0
T73	1529	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	612813	0	326
T1	1829	128	0	0
T2	10548	4261	0	2
T3	6281	57	0	0
T4	736	335	0	0
T5	26006	3738	0	2
T9	3037	73	0	0
T15	0	0	0	2
T20	0	0	0	2
T25	2222	11	0	0
T26	13021	821	0	0
T27	1874	128	0	0
T28	3882	29	0	0
T41	0	0	0	2
T42	0	0	0	2
T43	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	2704	0	120
T5	26006	0	0	0
T9	3037	3	0	1
T10	2584	0	0	0
T11	0	15	0	1
T16	2074	0	0	0
T25	2222	3	0	1
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	3	0	1
T29	826	0	0	0
T45	0	15	0	1
T46	0	15	0	1
T54	0	3	0	1
T55	0	7	0	1
T57	0	3	0	1
T64	0	15	0	1
T73	1529	0	0	0

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	162638	0	0
T4	736	381	0	0
T5	26006	0	0	0
T6	0	268	0	0
T7	0	612	0	0
T8	0	968	0	0
T9	3037	0	0	0
T14	0	1109	0	0
T15	0	9913	0	0
T16	2074	0	0	0
T17	0	20685	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1112	0	0
T67	0	612	0	0
T72	0	637	0	0
T73	1529	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	612813	0	326
T1	1829	128	0	0
T2	10548	4261	0	2
T3	6281	57	0	0
T4	736	335	0	0
T5	26006	3738	0	2
T9	3037	73	0	0
T15	0	0	0	2
T20	0	0	0	2
T25	2222	11	0	0
T26	13021	821	0	0
T27	1874	128	0	0
T28	3882	29	0	0
T41	0	0	0	2
T42	0	0	0	2
T43	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	2125	0	92
T5	26006	0	0	0
T9	3037	195	0	1
T10	2584	0	0	0
T11	0	63	0	1
T16	2074	0	0	0
T25	2222	3	0	1
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	53	0	1
T29	826	0	0	0
T45	0	3	0	1
T46	0	6	0	1
T54	0	44	0	1
T57	0	11	0	1
T73	1529	0	0	0
T76	0	4	0	0
T77	0	4	0	0
T78	0	0	0	1
T79	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	162638	0	0
T4	736	381	0	0
T5	26006	0	0	0
T6	0	268	0	0
T7	0	612	0	0
T8	0	968	0	0
T9	3037	0	0	0
T14	0	1109	0	0
T15	0	9913	0	0
T16	2074	0	0	0
T17	0	20685	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1112	0	0
T67	0	612	0	0
T72	0	637	0	0
T73	1529	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	612813	0	326
T1	1829	128	0	0
T2	10548	4261	0	2
T3	6281	57	0	0
T4	736	335	0	0
T5	26006	3738	0	2
T9	3037	73	0	0
T15	0	0	0	2
T20	0	0	0	2
T25	2222	11	0	0
T26	13021	821	0	0
T27	1874	128	0	0
T28	3882	29	0	0
T41	0	0	0	2
T42	0	0	0	2
T43	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	3856	0	101
T5	26006	0	0	0
T9	3037	3	0	1
T10	2584	0	0	0
T11	0	60	0	1
T16	2074	0	0	0
T25	2222	36	0	1
T26	13021	0	0	0
T27	1874	4	0	0
T28	3882	7	0	1
T29	826	0	0	0
T45	0	51	0	1
T46	0	25	0	1
T54	0	3	0	1
T73	1529	4	0	1
T76	0	4	0	1
T80	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	162638	0	0
T4	736	381	0	0
T5	26006	0	0	0
T6	0	268	0	0
T7	0	612	0	0
T8	0	968	0	0
T9	3037	0	0	0
T14	0	1109	0	0
T15	0	9913	0	0
T16	2074	0	0	0
T17	0	20685	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1112	0	0
T67	0	612	0	0
T72	0	637	0	0
T73	1529	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	612813	0	326
T1	1829	128	0	0
T2	10548	4261	0	2
T3	6281	57	0	0
T4	736	335	0	0
T5	26006	3738	0	2
T9	3037	73	0	0
T15	0	0	0	2
T20	0	0	0	2
T25	2222	11	0	0
T26	13021	821	0	0
T27	1874	128	0	0
T28	3882	29	0	0
T41	0	0	0	2
T42	0	0	0	2
T43	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	3221	0	92
T1	1829	8	0	1
T2	10548	0	0	0
T3	6281	0	0	0
T4	736	0	0	0
T5	26006	0	0	0
T9	3037	3	0	1
T11	0	0	0	1
T16	0	4	0	1
T20	0	1	0	0
T25	2222	15	0	1
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	34	0	1
T45	0	39	0	1
T46	0	3	0	1
T48	0	0	0	1
T54	0	3	0	1
T69	0	4	0	0

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	196351457	0	0
T1	1829	1738	0	0
T2	10548	10282	0	0
T3	6281	6218	0	0
T4	736	593	0	0
T5	26006	25143	0	0
T9	3037	2959	0	0
T25	2222	2155	0	0
T26	13021	12748	0	0
T27	1874	1815	0	0
T28	3882	3814	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196539342	162638	0	0
T4	736	381	0	0
T5	26006	0	0	0
T6	0	268	0	0
T7	0	612	0	0
T8	0	968	0	0
T9	3037	0	0	0
T14	0	1109	0	0
T15	0	9913	0	0
T16	2074	0	0	0
T17	0	20685	0	0
T25	2222	0	0	0
T26	13021	0	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T35	0	1112	0	0
T67	0	612	0	0
T72	0	637	0	0
T73	1529	0	0	0