Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	197058629	8900752	0	0
boot_gen_cmd_rd_A	197058629	39345	0	0
boot_ins_cmd_rd_A	197058629	45494	0	0
ctrl_rd_A	197058629	38317	0	0
err_code_test_rd_A	197058629	44176	0	0
intr_enable_rd_A	197058629	44486	0	0
max_num_reqs_between_reseeds_rd_A	197058629	40734	0	0
regwen_rd_A	197058629	45350	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197058629	8900752	0	0
T7	1647	0	0	0
T22	3493	0	0	0
T23	7141	0	0	0
T41	344128	141233	0	0
T42	0	40855	0	0
T43	0	142149	0	0
T70	1234	0	0	0
T71	0	325476	0	0
T74	1590	0	0	0
T86	0	98205	0	0
T87	8161	0	0	0
T219	0	474652	0	0
T220	0	178680	0	0
T221	0	338182	0	0
T222	0	160267	0	0
T223	0	162218	0	0
T224	966	0	0	0
T225	1274	0	0	0
T226	1315	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197058629	39345	0	0
T42	119621	1128	0	0
T43	256713	0	0	0
T71	795088	0	0	0
T83	1950	0	0	0
T86	0	2574	0	0
T88	12452	0	0	0
T89	1730	0	0	0
T101	2713	0	0	0
T129	2215	0	0	0
T220	0	5089	0	0
T227	0	2374	0	0
T228	0	1717	0	0
T229	0	1908	0	0
T230	0	2389	0	0
T231	0	5130	0	0
T232	0	2252	0	0
T233	0	5723	0	0
T234	6766	0	0	0
T235	2361	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197058629	45494	0	0
T42	119621	1249	0	0
T43	256713	0	0	0
T71	795088	0	0	0
T83	1950	0	0	0
T86	0	3043	0	0
T88	12452	0	0	0
T89	1730	0	0	0
T101	2713	0	0	0
T129	2215	0	0	0
T220	0	6337	0	0
T227	0	2482	0	0
T228	0	1876	0	0
T229	0	2208	0	0
T230	0	2811	0	0
T231	0	5686	0	0
T232	0	2539	0	0
T233	0	6668	0	0
T234	6766	0	0	0
T235	2361	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197058629	38317	0	0
T10	2584	0	0	0
T14	2133	0	0	0
T19	4084	0	0	0
T20	2228	0	0	0
T29	826	2	0	0
T31	0	4	0	0
T32	0	12	0	0
T42	0	1072	0	0
T44	2106	0	0	0
T45	2325	0	0	0
T46	1781	0	0	0
T73	1529	0	0	0
T86	0	2963	0	0
T90	1145	0	0	0
T220	0	5497	0	0
T227	0	1940	0	0
T228	0	1488	0	0
T229	0	1695	0	0
T236	0	7	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197058629	44176	0	0
T42	119621	1430	0	0
T43	256713	0	0	0
T71	795088	0	0	0
T83	1950	0	0	0
T86	0	3025	0	0
T88	12452	0	0	0
T89	1730	0	0	0
T101	2713	0	0	0
T129	2215	0	0	0
T220	0	5689	0	0
T227	0	2365	0	0
T228	0	1766	0	0
T229	0	2048	0	0
T230	0	2953	0	0
T231	0	5470	0	0
T232	0	2749	0	0
T233	0	6663	0	0
T234	6766	0	0	0
T235	2361	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197058629	44486	0	0
T5	26006	45	0	0
T9	3037	0	0	0
T10	2584	0	0	0
T16	2074	0	0	0
T19	4084	0	0	0
T26	13021	20	0	0
T27	1874	0	0	0
T28	3882	0	0	0
T29	826	0	0	0
T42	0	1591	0	0
T73	1529	0	0	0
T86	0	3013	0	0
T88	0	60	0	0
T220	0	5308	0	0
T227	0	2276	0	0
T228	0	1964	0	0
T237	0	50	0	0
T238	0	56	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197058629	40734	0	0
T42	119621	1151	0	0
T43	256713	0	0	0
T71	795088	0	0	0
T83	1950	0	0	0
T86	0	2947	0	0
T88	12452	0	0	0
T89	1730	0	0	0
T101	2713	0	0	0
T129	2215	0	0	0
T220	0	5470	0	0
T227	0	2195	0	0
T228	0	1687	0	0
T229	0	1961	0	0
T230	0	2561	0	0
T231	0	5176	0	0
T232	0	2342	0	0
T233	0	6079	0	0
T234	6766	0	0	0
T235	2361	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197058629	45350	0	0
T42	119621	1478	0	0
T43	256713	0	0	0
T71	795088	0	0	0
T83	1950	0	0	0
T86	0	3148	0	0
T88	12452	0	0	0
T89	1730	0	0	0
T101	2713	0	0	0
T129	2215	0	0	0
T220	0	6087	0	0
T227	0	2338	0	0
T228	0	1982	0	0
T229	0	2204	0	0
T230	0	2900	0	0
T231	0	5640	0	0
T232	0	2813	0	0
T233	0	6308	0	0
T234	6766	0	0	0
T235	2361	0	0	0