Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	79.67		66.67	100.00			72.34

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.59	98.25	93.25	91.10	86.63	95.50	96.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	87.22	99.92	91.98	48.52	86.63	97.42	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.77	95.02	97.16	99.53		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T5,T14,T20

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T21,T22	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T10,T23	Yes	T3,T10,T23	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T4,T6,T24	Yes	T4,T6,T24	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	INPUT
edn_i[1].edn_req	Yes	Yes	T2,T21,T17	Yes	T2,T21,T17	INPUT
edn_i[2].edn_req	Yes	Yes	T10,T17,T25	Yes	T10,T17,T25	INPUT
edn_i[3].edn_req	Yes	Yes	T26,T25,T12	Yes	T26,T25,T12	INPUT
edn_i[4].edn_req	Yes	Yes	T25,T27,T28	Yes	T25,T27,T28	INPUT
edn_i[5].edn_req	Yes	Yes	T3,T29,T16	Yes	T3,T29,T16	INPUT
edn_i[6].edn_req	Yes	Yes	T30,T26,T31	Yes	T30,T26,T31	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T32,T16	Yes	T1,T32,T16	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T21,T25,T12	Yes	T2,T21,T25	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T25,T28,T33	Yes	T25,T12,T27	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T2,T21,T17	Yes	T2,T21,T17	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T10,T17,T25	Yes	T10,T17,T25	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T10,T25,T28	Yes	T10,T17,T25	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T10,T17,T25	Yes	T10,T17,T25	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T26,T12,T33	Yes	T26,T12,T33	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T26,T12,T34	Yes	T26,T25,T12	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T26,T25,T12	Yes	T26,T25,T12	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T25,T27,T28	Yes	T25,T27,T28	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T25,T27,T28	Yes	T25,T27,T28	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T25,T27,T28	Yes	T25,T27,T28	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T3,T29,T16	Yes	T3,T29,T16	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T28,T35,T36	Yes	T29,T16,T28	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T3,T29,T16	Yes	T3,T29,T16	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T30,T26,T31	Yes	T30,T26,T31	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T37,T38,T39	Yes	T26,T28,T37	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T30,T26,T31	Yes	T30,T26,T31	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T10,T32	Yes	T2,T3,T10	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T10,T32,T16	Yes	T10,T32,T16	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T3,T21,T22	Yes	T3,T21,T22	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T5,T40,T14	Yes	T5,T40,T14	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T5,T40,T14	Yes	T5,T40,T14	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T6,T24	Yes	T4,T6,T24	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	34	72.34
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	34	72.34

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	224894250	224789514	0	0
CsrngAppIfOut_A	224894250	224789514	0	0
FpvSecCmCntAlertCheck_A	224894250	42	0	0
FpvSecCmGenCmdFifoRptrCheck_A	224894250	0	0	0
FpvSecCmGenCmdFifoWptrCheck_A	224894250	0	0	0
FpvSecCmMainFsmCheck_A	224894250	0	0	0
FpvSecCmRegWeOnehotCheck_A	224894250	0	0	0
FpvSecCmResCmdFifoRptrCheck_A	224894250	0	0	0
FpvSecCmResCmdFifoWptrCheck_A	224894250	0	0	0
IntrEdnCmdReqDoneKnownO_A	224894250	224789514	0	0
TlAReadyKnownO_A	224894250	224789514	0	0
TlDValidKnownO_A	224894250	224789514	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	224894250	0	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	224894250	0	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	224894250	0	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	224894250	0	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	224894250	0	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	224894250	0	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	224894250	0	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	224894250	484347	0	300
gen_edn_if_asserts[0].EdnDataStable_A	224894250	76302	0	436
gen_edn_if_asserts[0].EdnEndPointOut_A	224894250	224789514	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	224894250	86763	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	224894250	484347	0	300
gen_edn_if_asserts[1].EdnDataStable_A	224894250	3487	0	132
gen_edn_if_asserts[1].EdnEndPointOut_A	224894250	224789514	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	224894250	86763	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	224894250	484347	0	300
gen_edn_if_asserts[2].EdnDataStable_A	224894250	8104	0	117
gen_edn_if_asserts[2].EdnEndPointOut_A	224894250	224789514	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	224894250	86763	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	224894250	484347	0	300
gen_edn_if_asserts[3].EdnDataStable_A	224894250	4499	0	118
gen_edn_if_asserts[3].EdnEndPointOut_A	224894250	224789514	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	224894250	86763	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	224894250	484347	0	300
gen_edn_if_asserts[4].EdnDataStable_A	224894250	2622	0	89
gen_edn_if_asserts[4].EdnEndPointOut_A	224894250	224789514	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	224894250	86763	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	224894250	484347	0	300
gen_edn_if_asserts[5].EdnDataStable_A	224894250	2152	0	86
gen_edn_if_asserts[5].EdnEndPointOut_A	224894250	224789514	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	224894250	86763	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	224894250	484347	0	300
gen_edn_if_asserts[6].EdnDataStable_A	224894250	2709	0	76
gen_edn_if_asserts[6].EdnEndPointOut_A	224894250	224789514	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	224894250	86763	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	224789514	0	0
T1	2230	2174	0	0
T2	2343	2266	0	0
T3	2158	2107	0	0
T10	4681	4602	0	0
T16	1796	1715	0	0
T21	1985	1904	0	0
T22	2682	2584	0	0
T23	1598	1505	0	0
T29	1119	1025	0	0
T32	3515	3444	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	224789514	0	0
T1	2230	2174	0	0
T2	2343	2266	0	0
T3	2158	2107	0	0
T10	4681	4602	0	0
T16	1796	1715	0	0
T21	1985	1904	0	0
T22	2682	2584	0	0
T23	1598	1505	0	0
T29	1119	1025	0	0
T32	3515	3444	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	42	0	0
T7	0	1	0	0
T9	0	1	0	0
T11	2787	0	0	0
T14	795	1	0	0
T15	0	1	0	0
T18	1641	0	0	0
T20	2136	0	0	0
T25	4673	0	0	0
T26	1558	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	1851	0	0	0
T48	2271	0	0	0
T49	1751	0	0	0
T50	3489	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	224789514	0	0
T1	2230	2174	0	0
T2	2343	2266	0	0
T3	2158	2107	0	0
T10	4681	4602	0	0
T16	1796	1715	0	0
T21	1985	1904	0	0
T22	2682	2584	0	0
T23	1598	1505	0	0
T29	1119	1025	0	0
T32	3515	3444	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	224789514	0	0
T1	2230	2174	0	0
T2	2343	2266	0	0
T3	2158	2107	0	0
T10	4681	4602	0	0
T16	1796	1715	0	0
T21	1985	1904	0	0
T22	2682	2584	0	0
T23	1598	1505	0	0
T29	1119	1025	0	0
T32	3515	3444	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	224789514	0	0
T1	2230	2174	0	0
T2	2343	2266	0	0
T3	2158	2107	0	0
T10	4681	4602	0	0
T16	1796	1715	0	0
T21	1985	1904	0	0
T22	2682	2584	0	0
T23	1598	1505	0	0
T29	1119	1025	0	0
T32	3515	3444	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	484347	0	300
T1	2230	248	0	0
T2	2343	147	0	0
T3	2158	304	0	0
T4	0	0	0	2
T6	0	0	0	2
T10	4681	69	0	0
T16	1796	52	0	0
T17	0	0	0	2
T18	0	0	0	2
T21	1985	203	0	0
T22	2682	359	0	0
T23	1598	24	0	0
T29	1119	50	0	0
T31	0	0	0	2
T32	3515	175	0	0
T40	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	76302	0	436
T1	2230	8	0	1
T2	2343	4	0	0
T3	2158	0	0	0
T4	0	59	0	0
T5	0	1	0	0
T6	0	81	0	0
T10	4681	0	0	0
T11	0	65	0	1
T16	1796	44	0	1
T21	1985	0	0	0
T22	2682	8	0	1
T23	1598	3	0	1
T25	0	0	0	1
T26	0	0	0	1
T29	1119	0	0	0
T32	3515	62	0	1
T47	0	0	0	1
T48	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	224789514	0	0
T1	2230	2174	0	0
T2	2343	2266	0	0
T3	2158	2107	0	0
T10	4681	4602	0	0
T16	1796	1715	0	0
T21	1985	1904	0	0
T22	2682	2584	0	0
T23	1598	1505	0	0
T29	1119	1025	0	0
T32	3515	3444	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	86763	0	0
T5	648	25	0	0
T6	310418	0	0	0
T11	2787	0	0	0
T14	795	450	0	0
T17	3847	0	0	0
T18	1641	0	0	0
T20	0	411	0	0
T26	1558	0	0	0
T40	1431	0	0	0
T47	1851	0	0	0
T48	2271	0	0	0
T55	0	306	0	0
T56	0	22	0	0
T57	0	707	0	0
T58	0	329	0	0
T59	0	23	0	0
T60	0	1092	0	0
T61	0	1102	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	484347	0	300
T1	2230	248	0	0
T2	2343	147	0	0
T3	2158	304	0	0
T4	0	0	0	2
T6	0	0	0	2
T10	4681	69	0	0
T16	1796	52	0	0
T17	0	0	0	2
T18	0	0	0	2
T21	1985	203	0	0
T22	2682	359	0	0
T23	1598	24	0	0
T29	1119	50	0	0
T31	0	0	0	2
T32	3515	175	0	0
T40	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	3487	0	132
T2	2343	4	0	1
T3	2158	0	0	0
T4	251505	0	0	0
T10	4681	0	0	0
T12	0	3	0	1
T16	1796	0	0	0
T17	0	1	0	0
T21	1985	4	0	1
T22	2682	0	0	0
T23	1598	0	0	0
T25	0	54	0	1
T27	0	15	0	1
T28	0	30	0	1
T29	1119	0	0	0
T32	3515	0	0	0
T33	0	891	0	1
T35	0	0	0	1
T51	0	1	0	0
T62	0	4	0	1
T63	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	224789514	0	0
T1	2230	2174	0	0
T2	2343	2266	0	0
T3	2158	2107	0	0
T10	4681	4602	0	0
T16	1796	1715	0	0
T21	1985	1904	0	0
T22	2682	2584	0	0
T23	1598	1505	0	0
T29	1119	1025	0	0
T32	3515	3444	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	86763	0	0
T5	648	25	0	0
T6	310418	0	0	0
T11	2787	0	0	0
T14	795	450	0	0
T17	3847	0	0	0
T18	1641	0	0	0
T20	0	411	0	0
T26	1558	0	0	0
T40	1431	0	0	0
T47	1851	0	0	0
T48	2271	0	0	0
T55	0	306	0	0
T56	0	22	0	0
T57	0	707	0	0
T58	0	329	0	0
T59	0	23	0	0
T60	0	1092	0	0
T61	0	1102	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	484347	0	300
T1	2230	248	0	0
T2	2343	147	0	0
T3	2158	304	0	0
T4	0	0	0	2
T6	0	0	0	2
T10	4681	69	0	0
T16	1796	52	0	0
T17	0	0	0	2
T18	0	0	0	2
T21	1985	203	0	0
T22	2682	359	0	0
T23	1598	24	0	0
T29	1119	50	0	0
T31	0	0	0	2
T32	3515	175	0	0
T40	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	8104	0	117
T4	251505	0	0	0
T5	648	0	0	0
T10	4681	762	0	1
T13	0	0	0	1
T16	1796	0	0	0
T17	0	4	0	0
T22	2682	0	0	0
T23	1598	0	0	0
T25	0	59	0	1
T27	0	3	0	1
T28	0	21	0	1
T29	1119	0	0	0
T30	1108	0	0	0
T32	3515	0	0	0
T35	0	37	0	1
T36	0	3	0	1
T38	0	3	0	1
T39	0	0	0	1
T40	1431	0	0	0
T63	0	29	0	1
T64	0	4	0	0

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	224789514	0	0
T1	2230	2174	0	0
T2	2343	2266	0	0
T3	2158	2107	0	0
T10	4681	4602	0	0
T16	1796	1715	0	0
T21	1985	1904	0	0
T22	2682	2584	0	0
T23	1598	1505	0	0
T29	1119	1025	0	0
T32	3515	3444	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	86763	0	0
T5	648	25	0	0
T6	310418	0	0	0
T11	2787	0	0	0
T14	795	450	0	0
T17	3847	0	0	0
T18	1641	0	0	0
T20	0	411	0	0
T26	1558	0	0	0
T40	1431	0	0	0
T47	1851	0	0	0
T48	2271	0	0	0
T55	0	306	0	0
T56	0	22	0	0
T57	0	707	0	0
T58	0	329	0	0
T59	0	23	0	0
T60	0	1092	0	0
T61	0	1102	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	484347	0	300
T1	2230	248	0	0
T2	2343	147	0	0
T3	2158	304	0	0
T4	0	0	0	2
T6	0	0	0	2
T10	4681	69	0	0
T16	1796	52	0	0
T17	0	0	0	2
T18	0	0	0	2
T21	1985	203	0	0
T22	2682	359	0	0
T23	1598	24	0	0
T29	1119	50	0	0
T31	0	0	0	2
T32	3515	175	0	0
T40	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	4499	0	118
T12	3633	44	0	1
T20	2136	0	0	0
T24	108864	0	0	0
T25	4673	3	0	1
T26	1558	36	0	1
T31	1914	0	0	0
T33	0	3	0	1
T34	0	37	0	1
T35	0	8	0	1
T38	0	3	0	1
T49	1751	0	0	0
T50	3489	0	0	0
T51	3223	0	0	0
T63	0	15	0	1
T65	0	4	0	1
T66	0	3	0	1
T67	1537	0	0	0

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	224789514	0	0
T1	2230	2174	0	0
T2	2343	2266	0	0
T3	2158	2107	0	0
T10	4681	4602	0	0
T16	1796	1715	0	0
T21	1985	1904	0	0
T22	2682	2584	0	0
T23	1598	1505	0	0
T29	1119	1025	0	0
T32	3515	3444	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	86763	0	0
T5	648	25	0	0
T6	310418	0	0	0
T11	2787	0	0	0
T14	795	450	0	0
T17	3847	0	0	0
T18	1641	0	0	0
T20	0	411	0	0
T26	1558	0	0	0
T40	1431	0	0	0
T47	1851	0	0	0
T48	2271	0	0	0
T55	0	306	0	0
T56	0	22	0	0
T57	0	707	0	0
T58	0	329	0	0
T59	0	23	0	0
T60	0	1092	0	0
T61	0	1102	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	484347	0	300
T1	2230	248	0	0
T2	2343	147	0	0
T3	2158	304	0	0
T4	0	0	0	2
T6	0	0	0	2
T10	4681	69	0	0
T16	1796	52	0	0
T17	0	0	0	2
T18	0	0	0	2
T21	1985	203	0	0
T22	2682	359	0	0
T23	1598	24	0	0
T29	1119	50	0	0
T31	0	0	0	2
T32	3515	175	0	0
T40	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	2622	0	89
T12	3633	0	0	0
T13	0	61	0	1
T24	108864	0	0	0
T25	4673	22	0	1
T27	0	41	0	1
T28	0	19	0	1
T31	1914	0	0	0
T36	0	3	0	1
T38	0	3	0	1
T39	0	13	0	1
T49	1751	0	0	0
T50	3489	0	0	0
T51	3223	0	0	0
T55	781	0	0	0
T66	0	3	0	1
T67	1537	0	0	0
T68	0	1	0	0
T69	0	4	0	1
T70	2648	0	0	0
T71	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	224789514	0	0
T1	2230	2174	0	0
T2	2343	2266	0	0
T3	2158	2107	0	0
T10	4681	4602	0	0
T16	1796	1715	0	0
T21	1985	1904	0	0
T22	2682	2584	0	0
T23	1598	1505	0	0
T29	1119	1025	0	0
T32	3515	3444	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	86763	0	0
T5	648	25	0	0
T6	310418	0	0	0
T11	2787	0	0	0
T14	795	450	0	0
T17	3847	0	0	0
T18	1641	0	0	0
T20	0	411	0	0
T26	1558	0	0	0
T40	1431	0	0	0
T47	1851	0	0	0
T48	2271	0	0	0
T55	0	306	0	0
T56	0	22	0	0
T57	0	707	0	0
T58	0	329	0	0
T59	0	23	0	0
T60	0	1092	0	0
T61	0	1102	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	484347	0	300
T1	2230	248	0	0
T2	2343	147	0	0
T3	2158	304	0	0
T4	0	0	0	2
T6	0	0	0	2
T10	4681	69	0	0
T16	1796	52	0	0
T17	0	0	0	2
T18	0	0	0	2
T21	1985	203	0	0
T22	2682	359	0	0
T23	1598	24	0	0
T29	1119	50	0	0
T31	0	0	0	2
T32	3515	175	0	0
T40	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	2152	0	86
T3	2158	4	0	1
T4	251505	0	0	0
T10	4681	0	0	0
T16	1796	15	0	1
T18	0	4	0	0
T21	1985	0	0	0
T22	2682	0	0	0
T23	1598	0	0	0
T28	0	48	0	1
T29	1119	3	0	1
T30	1108	0	0	0
T32	3515	0	0	0
T33	0	3	0	1
T35	0	51	0	1
T36	0	55	0	1
T38	0	0	0	1
T72	0	3	0	1
T73	0	4	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	224789514	0	0
T1	2230	2174	0	0
T2	2343	2266	0	0
T3	2158	2107	0	0
T10	4681	4602	0	0
T16	1796	1715	0	0
T21	1985	1904	0	0
T22	2682	2584	0	0
T23	1598	1505	0	0
T29	1119	1025	0	0
T32	3515	3444	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	86763	0	0
T5	648	25	0	0
T6	310418	0	0	0
T11	2787	0	0	0
T14	795	450	0	0
T17	3847	0	0	0
T18	1641	0	0	0
T20	0	411	0	0
T26	1558	0	0	0
T40	1431	0	0	0
T47	1851	0	0	0
T48	2271	0	0	0
T55	0	306	0	0
T56	0	22	0	0
T57	0	707	0	0
T58	0	329	0	0
T59	0	23	0	0
T60	0	1092	0	0
T61	0	1102	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	484347	0	300
T1	2230	248	0	0
T2	2343	147	0	0
T3	2158	304	0	0
T4	0	0	0	2
T6	0	0	0	2
T10	4681	69	0	0
T16	1796	52	0	0
T17	0	0	0	2
T18	0	0	0	2
T21	1985	203	0	0
T22	2682	359	0	0
T23	1598	24	0	0
T29	1119	50	0	0
T31	0	0	0	2
T32	3515	175	0	0
T40	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	2709	0	76
T5	648	0	0	0
T6	310418	0	0	0
T11	2787	0	0	0
T14	795	0	0	0
T17	3847	0	0	0
T18	1641	0	0	0
T26	0	3	0	1
T28	0	3	0	1
T30	1108	3	0	1
T31	0	4	0	0
T35	0	3	0	1
T37	0	11	0	1
T38	0	47	0	1
T40	1431	0	0	0
T47	1851	0	0	0
T48	2271	0	0	0
T66	0	3	0	1
T67	0	3	0	1
T74	0	4	0	0
T75	0	0	0	1
T76	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	224789514	0	0
T1	2230	2174	0	0
T2	2343	2266	0	0
T3	2158	2107	0	0
T10	4681	4602	0	0
T16	1796	1715	0	0
T21	1985	1904	0	0
T22	2682	2584	0	0
T23	1598	1505	0	0
T29	1119	1025	0	0
T32	3515	3444	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224894250	86763	0	0
T5	648	25	0	0
T6	310418	0	0	0
T11	2787	0	0	0
T14	795	450	0	0
T17	3847	0	0	0
T18	1641	0	0	0
T20	0	411	0	0
T26	1558	0	0	0
T40	1431	0	0	0
T47	1851	0	0	0
T48	2271	0	0	0
T55	0	306	0	0
T56	0	22	0	0
T57	0	707	0	0
T58	0	329	0	0
T59	0	23	0	0
T60	0	1092	0	0
T61	0	1102	0	0