Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.67		66.67	100.00			72.34	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	225419369	9593013	0	0
boot_gen_cmd_rd_A	225419369	94025	0	0
boot_ins_cmd_rd_A	225419369	108061	0	0
ctrl_rd_A	225419369	94915	0	0
err_code_test_rd_A	225419369	109508	0	0
intr_enable_rd_A	225419369	103760	0	0
max_num_reqs_between_reseeds_rd_A	225419369	96915	0	0
regwen_rd_A	225419369	108966	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225419369	9593013	0	0
T4	251505	90754	0	0
T5	648	0	0	0
T6	310418	114352	0	0
T11	2787	0	0	0
T14	795	0	0	0
T17	3847	0	0	0
T24	0	38966	0	0
T30	1108	0	0	0
T40	1431	0	0	0
T47	1851	0	0	0
T48	2271	0	0	0
T91	0	161182	0	0
T92	0	181369	0	0
T93	0	157211	0	0
T216	0	84998	0	0
T217	0	138855	0	0
T218	0	105449	0	0
T219	0	134986	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225419369	94025	0	0
T4	251505	1389	0	0
T5	648	0	0	0
T6	310418	1443	0	0
T11	2787	0	0	0
T14	795	0	0	0
T17	3847	0	0	0
T24	0	610	0	0
T30	1108	0	0	0
T40	1431	0	0	0
T47	1851	0	0	0
T48	2271	0	0	0
T93	0	4727	0	0
T216	0	1286	0	0
T220	0	11225	0	0
T221	0	4120	0	0
T222	0	6735	0	0
T223	0	7590	0	0
T224	0	1793	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225419369	108061	0	0
T4	251505	1551	0	0
T5	648	0	0	0
T6	310418	2072	0	0
T11	2787	0	0	0
T14	795	0	0	0
T17	3847	0	0	0
T24	0	727	0	0
T30	1108	0	0	0
T40	1431	0	0	0
T47	1851	0	0	0
T48	2271	0	0	0
T93	0	5455	0	0
T216	0	1469	0	0
T220	0	12956	0	0
T221	0	4921	0	0
T222	0	7388	0	0
T223	0	8195	0	0
T224	0	2189	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225419369	94915	0	0
T4	251505	1310	0	0
T5	648	0	0	0
T6	310418	1671	0	0
T11	2787	0	0	0
T14	795	0	0	0
T17	3847	0	0	0
T24	0	607	0	0
T30	1108	0	0	0
T40	1431	0	0	0
T47	1851	0	0	0
T48	2271	0	0	0
T57	0	3	0	0
T58	0	2	0	0
T93	0	4606	0	0
T117	0	2	0	0
T170	0	8	0	0
T216	0	1127	0	0
T225	0	4	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225419369	109508	0	0
T4	251505	1912	0	0
T5	648	0	0	0
T6	310418	1973	0	0
T11	2787	0	0	0
T14	795	0	0	0
T17	3847	0	0	0
T24	0	574	0	0
T30	1108	0	0	0
T40	1431	0	0	0
T47	1851	0	0	0
T48	2271	0	0	0
T93	0	5415	0	0
T216	0	1477	0	0
T220	0	13426	0	0
T221	0	4799	0	0
T222	0	7784	0	0
T223	0	8191	0	0
T224	0	2208	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225419369	103760	0	0
T4	251505	1378	0	0
T5	648	0	0	0
T6	310418	1801	0	0
T11	2787	0	0	0
T14	795	0	0	0
T17	3847	0	0	0
T24	0	784	0	0
T30	1108	0	0	0
T40	1431	0	0	0
T47	1851	0	0	0
T48	2271	0	0	0
T52	0	67	0	0
T93	0	5504	0	0
T216	0	1481	0	0
T220	0	11401	0	0
T221	0	4496	0	0
T225	0	29	0	0
T226	0	134	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225419369	96915	0	0
T4	251505	1386	0	0
T5	648	0	0	0
T6	310418	1620	0	0
T11	2787	0	0	0
T14	795	0	0	0
T17	3847	0	0	0
T24	0	561	0	0
T30	1108	0	0	0
T40	1431	0	0	0
T47	1851	0	0	0
T48	2271	0	0	0
T93	0	4408	0	0
T216	0	1285	0	0
T220	0	11325	0	0
T221	0	4353	0	0
T222	0	7068	0	0
T223	0	7301	0	0
T224	0	1841	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225419369	108966	0	0
T4	251505	1506	0	0
T5	648	0	0	0
T6	310418	2039	0	0
T11	2787	0	0	0
T14	795	0	0	0
T17	3847	0	0	0
T24	0	822	0	0
T30	1108	0	0	0
T40	1431	0	0	0
T47	1851	0	0	0
T48	2271	0	0	0
T93	0	5298	0	0
T216	0	1492	0	0
T220	0	12919	0	0
T221	0	5029	0	0
T222	0	7482	0	0
T223	0	7941	0	0
T224	0	2038	0	0