Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	79.67		66.67	100.00			72.34

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.05	98.25	93.31	90.85	89.53	95.50	96.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	87.48	99.92	92.06	47.04	89.53	97.42	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.77	95.02	97.16	99.53		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T8

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T4,T5

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T18,T4	Yes	T3,T18,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T19	Yes	T1,T3,T19	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T20	Yes	T1,T3,T20	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T21,T22,T23	Yes	T21,T22,T23	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T19	Yes	T1,T3,T19	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T20	Yes	T1,T3,T20	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T19,T24	Yes	T1,T19,T24	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[2].edn_req	Yes	Yes	T25,T26,T13	Yes	T25,T26,T13	INPUT
edn_i[3].edn_req	Yes	Yes	T25,T26,T15	Yes	T25,T26,T15	INPUT
edn_i[4].edn_req	Yes	Yes	T25,T27,T28	Yes	T25,T27,T28	INPUT
edn_i[5].edn_req	Yes	Yes	T25,T29,T30	Yes	T25,T29,T30	INPUT
edn_i[6].edn_req	Yes	Yes	T31,T32,T25	Yes	T31,T32,T25	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T24,T18,T33	Yes	T1,T19,T24	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T24,T12,T31	Yes	T1,T24,T12	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T19,T24	Yes	T1,T19,T24	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T17,T34,T35	Yes	T8,T17,T30	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T25,T26,T30	Yes	T25,T26,T30	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T26,T36,T9	Yes	T26,T30,T36	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T25,T26,T30	Yes	T25,T26,T30	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T25,T26,T30	Yes	T25,T26,T30	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T25,T26,T30	Yes	T25,T26,T30	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T25,T26,T15	Yes	T25,T26,T15	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T25,T27,T28	Yes	T25,T27,T28	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T27,T36,T37	Yes	T25,T27,T28	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T25,T27,T28	Yes	T25,T27,T28	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T29,T30,T36	Yes	T25,T29,T30	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T30,T38,T35	Yes	T25,T29,T30	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T25,T29,T30	Yes	T25,T29,T30	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T31,T32,T39	Yes	T31,T32,T25	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T40,T36,T37	Yes	T31,T32,T25	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T31,T32,T25	Yes	T31,T32,T25	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T24,T33,T12	Yes	T1,T24,T12	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T24,T12,T21	Yes	T1,T24,T12	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T3,T19	Yes	T1,T3,T19	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T1,T3,T31	Yes	T1,T3,T31	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T3,T20	Yes	T1,T3,T20	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T20,T4	Yes	T2,T20,T4	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T3,T20	Yes	T1,T3,T20	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T20,T4	Yes	T2,T20,T4	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T18,T21,T41	Yes	T18,T21,T41	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T18,T21,T41	Yes	T18,T21,T41	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	34	72.34
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	34	72.34

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	216344672	216237566	0	0
CsrngAppIfOut_A	216344672	216237566	0	0
FpvSecCmCntAlertCheck_A	216344672	44	0	0
FpvSecCmGenCmdFifoRptrCheck_A	216344672	0	0	0
FpvSecCmGenCmdFifoWptrCheck_A	216344672	0	0	0
FpvSecCmMainFsmCheck_A	216344672	0	0	0
FpvSecCmRegWeOnehotCheck_A	216344672	0	0	0
FpvSecCmResCmdFifoRptrCheck_A	216344672	0	0	0
FpvSecCmResCmdFifoWptrCheck_A	216344672	0	0	0
IntrEdnCmdReqDoneKnownO_A	216344672	216237566	0	0
TlAReadyKnownO_A	216344672	216237566	0	0
TlDValidKnownO_A	216344672	216237566	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	216344672	0	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	216344672	0	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	216344672	0	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	216344672	0	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	216344672	0	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	216344672	0	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	216344672	0	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	216344672	506798	0	310
gen_edn_if_asserts[0].EdnDataStable_A	216344672	69349	0	424
gen_edn_if_asserts[0].EdnEndPointOut_A	216344672	216237566	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	216344672	87828	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	216344672	506798	0	310
gen_edn_if_asserts[1].EdnDataStable_A	216344672	7458	0	138
gen_edn_if_asserts[1].EdnEndPointOut_A	216344672	216237566	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	216344672	87828	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	216344672	506798	0	310
gen_edn_if_asserts[2].EdnDataStable_A	216344672	51726	0	110
gen_edn_if_asserts[2].EdnEndPointOut_A	216344672	216237566	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	216344672	87828	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	216344672	506798	0	310
gen_edn_if_asserts[3].EdnDataStable_A	216344672	52951	0	128
gen_edn_if_asserts[3].EdnEndPointOut_A	216344672	216237566	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	216344672	87828	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	216344672	506798	0	310
gen_edn_if_asserts[4].EdnDataStable_A	216344672	2836	0	113
gen_edn_if_asserts[4].EdnEndPointOut_A	216344672	216237566	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	216344672	87828	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	216344672	506798	0	310
gen_edn_if_asserts[5].EdnDataStable_A	216344672	1971	0	94
gen_edn_if_asserts[5].EdnEndPointOut_A	216344672	216237566	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	216344672	87828	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	216344672	506798	0	310
gen_edn_if_asserts[6].EdnDataStable_A	216344672	4580	0	102
gen_edn_if_asserts[6].EdnEndPointOut_A	216344672	216237566	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	216344672	87828	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	216237566	0	0
T1	2576	2485	0	0
T2	2046	1879	0	0
T3	2503	2429	0	0
T4	2930	2769	0	0
T8	1776	1718	0	0
T18	6169	6070	0	0
T19	3456	3369	0	0
T20	1306	1215	0	0
T24	1496	1417	0	0
T33	1042	960	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	216237566	0	0
T1	2576	2485	0	0
T2	2046	1879	0	0
T3	2503	2429	0	0
T4	2930	2769	0	0
T8	1776	1718	0	0
T18	6169	6070	0	0
T19	3456	3369	0	0
T20	1306	1215	0	0
T24	1496	1417	0	0
T33	1042	960	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	44	0	0
T4	2930	1	0	0
T5	1829	0	0	0
T6	0	1	0	0
T8	1776	0	0	0
T12	6398	0	0	0
T13	0	1	0	0
T21	297083	0	0	0
T25	1797	0	0	0
T31	1844	0	0	0
T32	1193	0	0	0
T33	1042	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	827	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	216237566	0	0
T1	2576	2485	0	0
T2	2046	1879	0	0
T3	2503	2429	0	0
T4	2930	2769	0	0
T8	1776	1718	0	0
T18	6169	6070	0	0
T19	3456	3369	0	0
T20	1306	1215	0	0
T24	1496	1417	0	0
T33	1042	960	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	216237566	0	0
T1	2576	2485	0	0
T2	2046	1879	0	0
T3	2503	2429	0	0
T4	2930	2769	0	0
T8	1776	1718	0	0
T18	6169	6070	0	0
T19	3456	3369	0	0
T20	1306	1215	0	0
T24	1496	1417	0	0
T33	1042	960	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	216237566	0	0
T1	2576	2485	0	0
T2	2046	1879	0	0
T3	2503	2429	0	0
T4	2930	2769	0	0
T8	1776	1718	0	0
T18	6169	6070	0	0
T19	3456	3369	0	0
T20	1306	1215	0	0
T24	1496	1417	0	0
T33	1042	960	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	506798	0	310
T1	2576	240	0	0
T2	2046	1171	0	0
T3	2503	497	0	0
T4	2930	1246	0	0
T8	1776	282	0	0
T15	0	0	0	2
T18	6169	12	0	0
T19	3456	20	0	0
T20	1306	1213	0	2
T21	0	0	0	2
T24	1496	18	0	0
T33	1042	64	0	0
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	69349	0	424
T1	2576	4	0	1
T2	2046	0	0	0
T3	2503	0	0	0
T4	2930	0	0	0
T8	1776	0	0	0
T12	0	1118	0	1
T14	0	0	0	1
T18	6169	7	0	1
T19	3456	3	0	1
T20	1306	0	0	0
T21	0	64	0	0
T24	1496	64	0	1
T25	0	7	0	1
T27	0	4	0	1
T31	0	4	0	0
T33	1042	3	0	1
T57	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	216237566	0	0
T1	2576	2485	0	0
T2	2046	1879	0	0
T3	2503	2429	0	0
T4	2930	2769	0	0
T8	1776	1718	0	0
T18	6169	6070	0	0
T19	3456	3369	0	0
T20	1306	1215	0	0
T24	1496	1417	0	0
T33	1042	960	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	87828	0	0
T2	2046	1183	0	0
T3	2503	0	0	0
T4	2930	856	0	0
T5	0	404	0	0
T6	0	203	0	0
T8	1776	0	0	0
T12	6398	0	0	0
T13	0	399	0	0
T18	6169	0	0	0
T19	3456	0	0	0
T20	1306	0	0	0
T24	1496	0	0	0
T33	1042	0	0	0
T42	0	299	0	0
T49	0	395	0	0
T58	0	628	0	0
T59	0	636	0	0
T60	0	232	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	506798	0	310
T1	2576	240	0	0
T2	2046	1171	0	0
T3	2503	497	0	0
T4	2930	1246	0	0
T8	1776	282	0	0
T15	0	0	0	2
T18	6169	12	0	0
T19	3456	20	0	0
T20	1306	1213	0	2
T21	0	0	0	2
T24	1496	18	0	0
T33	1042	64	0	0
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	7458	0	138
T1	2576	4	0	0
T2	2046	0	0	0
T3	2503	4	0	1
T4	2930	0	0	0
T8	1776	4	0	1
T17	0	50	0	1
T18	6169	0	0	0
T19	3456	0	0	0
T20	1306	0	0	0
T24	1496	0	0	0
T25	0	3	0	1
T30	0	10	0	1
T33	1042	0	0	0
T34	0	11	0	1
T35	0	0	0	1
T36	0	3	0	1
T38	0	3	0	1
T61	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	216237566	0	0
T1	2576	2485	0	0
T2	2046	1879	0	0
T3	2503	2429	0	0
T4	2930	2769	0	0
T8	1776	1718	0	0
T18	6169	6070	0	0
T19	3456	3369	0	0
T20	1306	1215	0	0
T24	1496	1417	0	0
T33	1042	960	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	87828	0	0
T2	2046	1183	0	0
T3	2503	0	0	0
T4	2930	856	0	0
T5	0	404	0	0
T6	0	203	0	0
T8	1776	0	0	0
T12	6398	0	0	0
T13	0	399	0	0
T18	6169	0	0	0
T19	3456	0	0	0
T20	1306	0	0	0
T24	1496	0	0	0
T33	1042	0	0	0
T42	0	299	0	0
T49	0	395	0	0
T58	0	628	0	0
T59	0	636	0	0
T60	0	232	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	506798	0	310
T1	2576	240	0	0
T2	2046	1171	0	0
T3	2503	497	0	0
T4	2930	1246	0	0
T8	1776	282	0	0
T15	0	0	0	2
T18	6169	12	0	0
T19	3456	20	0	0
T20	1306	1213	0	2
T21	0	0	0	2
T24	1496	18	0	0
T33	1042	64	0	0
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	51726	0	110
T9	0	44	0	1
T14	3106	0	0	0
T17	1929	0	0	0
T25	1797	3	0	1
T26	0	19	0	1
T27	2258	0	0	0
T28	2617	0	0	0
T30	0	3	0	1
T35	0	3	0	1
T36	0	55	0	1
T39	1947	0	0	0
T41	11873	0	0	0
T50	2045	0	0	0
T51	2041	0	0	0
T55	0	4	0	0
T57	1850	0	0	0
T61	0	3	0	1
T62	0	3	0	1
T63	0	1	0	0
T64	0	0	0	1
T65	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	216237566	0	0
T1	2576	2485	0	0
T2	2046	1879	0	0
T3	2503	2429	0	0
T4	2930	2769	0	0
T8	1776	1718	0	0
T18	6169	6070	0	0
T19	3456	3369	0	0
T20	1306	1215	0	0
T24	1496	1417	0	0
T33	1042	960	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	87828	0	0
T2	2046	1183	0	0
T3	2503	0	0	0
T4	2930	856	0	0
T5	0	404	0	0
T6	0	203	0	0
T8	1776	0	0	0
T12	6398	0	0	0
T13	0	399	0	0
T18	6169	0	0	0
T19	3456	0	0	0
T20	1306	0	0	0
T24	1496	0	0	0
T33	1042	0	0	0
T42	0	299	0	0
T49	0	395	0	0
T58	0	628	0	0
T59	0	636	0	0
T60	0	232	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	506798	0	310
T1	2576	240	0	0
T2	2046	1171	0	0
T3	2503	497	0	0
T4	2930	1246	0	0
T8	1776	282	0	0
T15	0	0	0	2
T18	6169	12	0	0
T19	3456	20	0	0
T20	1306	1213	0	2
T21	0	0	0	2
T24	1496	18	0	0
T33	1042	64	0	0
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	52951	0	128
T9	0	15	0	1
T14	3106	0	0	0
T15	0	1	0	0
T17	1929	0	0	0
T25	1797	41	0	1
T26	0	41	0	1
T27	2258	0	0	0
T28	2617	0	0	0
T30	0	58	0	1
T36	0	36	0	1
T37	0	3	0	1
T38	0	3	0	1
T39	1947	0	0	0
T41	11873	0	0	0
T50	2045	0	0	0
T51	2041	0	0	0
T57	1850	0	0	0
T61	0	24	0	1
T66	0	3	0	1
T67	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	216237566	0	0
T1	2576	2485	0	0
T2	2046	1879	0	0
T3	2503	2429	0	0
T4	2930	2769	0	0
T8	1776	1718	0	0
T18	6169	6070	0	0
T19	3456	3369	0	0
T20	1306	1215	0	0
T24	1496	1417	0	0
T33	1042	960	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	87828	0	0
T2	2046	1183	0	0
T3	2503	0	0	0
T4	2930	856	0	0
T5	0	404	0	0
T6	0	203	0	0
T8	1776	0	0	0
T12	6398	0	0	0
T13	0	399	0	0
T18	6169	0	0	0
T19	3456	0	0	0
T20	1306	0	0	0
T24	1496	0	0	0
T33	1042	0	0	0
T42	0	299	0	0
T49	0	395	0	0
T58	0	628	0	0
T59	0	636	0	0
T60	0	232	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	506798	0	310
T1	2576	240	0	0
T2	2046	1171	0	0
T3	2503	497	0	0
T4	2930	1246	0	0
T8	1776	282	0	0
T15	0	0	0	2
T18	6169	12	0	0
T19	3456	20	0	0
T20	1306	1213	0	2
T21	0	0	0	2
T24	1496	18	0	0
T33	1042	64	0	0
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	2836	0	113
T14	3106	0	0	0
T17	1929	0	0	0
T25	1797	3	0	1
T27	2258	4	0	0
T28	2617	3	0	1
T30	0	3	0	1
T34	0	3	0	1
T35	0	3	0	1
T36	0	34	0	1
T37	0	0	0	1
T39	1947	0	0	0
T40	0	4	0	1
T41	11873	0	0	0
T50	2045	0	0	0
T51	2041	0	0	0
T57	1850	0	0	0
T61	0	10	0	1
T64	0	0	0	1
T68	0	4	0	0

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	216237566	0	0
T1	2576	2485	0	0
T2	2046	1879	0	0
T3	2503	2429	0	0
T4	2930	2769	0	0
T8	1776	1718	0	0
T18	6169	6070	0	0
T19	3456	3369	0	0
T20	1306	1215	0	0
T24	1496	1417	0	0
T33	1042	960	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	87828	0	0
T2	2046	1183	0	0
T3	2503	0	0	0
T4	2930	856	0	0
T5	0	404	0	0
T6	0	203	0	0
T8	1776	0	0	0
T12	6398	0	0	0
T13	0	399	0	0
T18	6169	0	0	0
T19	3456	0	0	0
T20	1306	0	0	0
T24	1496	0	0	0
T33	1042	0	0	0
T42	0	299	0	0
T49	0	395	0	0
T58	0	628	0	0
T59	0	636	0	0
T60	0	232	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	506798	0	310
T1	2576	240	0	0
T2	2046	1171	0	0
T3	2503	497	0	0
T4	2930	1246	0	0
T8	1776	282	0	0
T15	0	0	0	2
T18	6169	12	0	0
T19	3456	20	0	0
T20	1306	1213	0	2
T21	0	0	0	2
T24	1496	18	0	0
T33	1042	64	0	0
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	1971	0	94
T14	3106	0	0	0
T17	1929	0	0	0
T25	1797	3	0	1
T27	2258	0	0	0
T28	2617	0	0	0
T29	0	8	0	1
T30	0	37	0	1
T34	0	3	0	1
T35	0	46	0	1
T36	0	3	0	1
T38	0	51	0	1
T39	1947	0	0	0
T41	11873	0	0	0
T50	2045	0	0	0
T51	2041	0	0	0
T57	1850	0	0	0
T64	0	3	0	1
T69	0	1	0	0
T70	0	19	0	1
T71	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	216237566	0	0
T1	2576	2485	0	0
T2	2046	1879	0	0
T3	2503	2429	0	0
T4	2930	2769	0	0
T8	1776	1718	0	0
T18	6169	6070	0	0
T19	3456	3369	0	0
T20	1306	1215	0	0
T24	1496	1417	0	0
T33	1042	960	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	87828	0	0
T2	2046	1183	0	0
T3	2503	0	0	0
T4	2930	856	0	0
T5	0	404	0	0
T6	0	203	0	0
T8	1776	0	0	0
T12	6398	0	0	0
T13	0	399	0	0
T18	6169	0	0	0
T19	3456	0	0	0
T20	1306	0	0	0
T24	1496	0	0	0
T33	1042	0	0	0
T42	0	299	0	0
T49	0	395	0	0
T58	0	628	0	0
T59	0	636	0	0
T60	0	232	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	506798	0	310
T1	2576	240	0	0
T2	2046	1171	0	0
T3	2503	497	0	0
T4	2930	1246	0	0
T8	1776	282	0	0
T15	0	0	0	2
T18	6169	12	0	0
T19	3456	20	0	0
T20	1306	1213	0	2
T21	0	0	0	2
T24	1496	18	0	0
T33	1042	64	0	0
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	4580	0	102
T7	0	1	0	0
T14	3106	0	0	0
T21	297083	0	0	0
T25	1797	3	0	1
T27	2258	0	0	0
T30	0	3	0	1
T31	1844	4	0	1
T32	1193	3	0	1
T34	0	3	0	1
T36	0	24	0	1
T37	0	0	0	1
T39	0	4	0	1
T40	0	4	0	0
T41	11873	0	0	0
T49	827	0	0	0
T50	2045	0	0	0
T57	1850	0	0	0
T64	0	0	0	1
T72	0	4	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	216237566	0	0
T1	2576	2485	0	0
T2	2046	1879	0	0
T3	2503	2429	0	0
T4	2930	2769	0	0
T8	1776	1718	0	0
T18	6169	6070	0	0
T19	3456	3369	0	0
T20	1306	1215	0	0
T24	1496	1417	0	0
T33	1042	960	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216344672	87828	0	0
T2	2046	1183	0	0
T3	2503	0	0	0
T4	2930	856	0	0
T5	0	404	0	0
T6	0	203	0	0
T8	1776	0	0	0
T12	6398	0	0	0
T13	0	399	0	0
T18	6169	0	0	0
T19	3456	0	0	0
T20	1306	0	0	0
T24	1496	0	0	0
T33	1042	0	0	0
T42	0	299	0	0
T49	0	395	0	0
T58	0	628	0	0
T59	0	636	0	0
T60	0	232	0	0