Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.67		66.67	100.00			72.34	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	216856779	9423534	0	0
boot_gen_cmd_rd_A	216856779	67327	0	0
boot_ins_cmd_rd_A	216856779	76486	0	0
ctrl_rd_A	216856779	68803	0	0
err_code_test_rd_A	216856779	78627	0	0
intr_enable_rd_A	216856779	75927	0	0
max_num_reqs_between_reseeds_rd_A	216856779	68824	0	0
regwen_rd_A	216856779	77886	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216856779	9423534	0	0
T14	3106	0	0	0
T17	1929	0	0	0
T21	297083	107185	0	0
T22	0	220732	0	0
T23	0	233588	0	0
T25	1797	0	0	0
T27	2258	0	0	0
T39	1947	0	0	0
T41	11873	0	0	0
T50	2045	0	0	0
T51	2041	0	0	0
T57	1850	0	0	0
T133	0	119684	0	0
T135	0	267822	0	0
T136	0	168764	0	0
T227	0	85829	0	0
T228	0	142173	0	0
T229	0	285720	0	0
T230	0	246070	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216856779	67327	0	0
T14	3106	0	0	0
T17	1929	0	0	0
T21	297083	1631	0	0
T25	1797	0	0	0
T27	2258	0	0	0
T39	1947	0	0	0
T41	11873	0	0	0
T50	2045	0	0	0
T51	2041	0	0	0
T57	1850	0	0	0
T227	0	2552	0	0
T231	0	4808	0	0
T232	0	1844	0	0
T233	0	3045	0	0
T234	0	5178	0	0
T235	0	2902	0	0
T236	0	2937	0	0
T237	0	2743	0	0
T238	0	5694	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216856779	76486	0	0
T14	3106	0	0	0
T17	1929	0	0	0
T21	297083	1781	0	0
T25	1797	0	0	0
T27	2258	0	0	0
T39	1947	0	0	0
T41	11873	0	0	0
T50	2045	0	0	0
T51	2041	0	0	0
T57	1850	0	0	0
T227	0	2506	0	0
T231	0	5649	0	0
T232	0	2317	0	0
T233	0	3769	0	0
T234	0	6177	0	0
T235	0	3594	0	0
T236	0	3531	0	0
T237	0	3185	0	0
T238	0	5804	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216856779	68803	0	0
T14	3106	0	0	0
T17	1929	0	0	0
T21	297083	1716	0	0
T25	1797	0	0	0
T27	2258	0	0	0
T39	1947	0	0	0
T41	11873	0	0	0
T42	0	1	0	0
T50	2045	0	0	0
T51	2041	0	0	0
T57	1850	0	0	0
T68	0	1	0	0
T73	0	4	0	0
T187	0	8	0	0
T227	0	2388	0	0
T231	0	5192	0	0
T239	0	1	0	0
T240	0	9	0	0
T241	0	14	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216856779	78627	0	0
T14	3106	0	0	0
T17	1929	0	0	0
T21	297083	2059	0	0
T25	1797	0	0	0
T27	2258	0	0	0
T39	1947	0	0	0
T41	11873	0	0	0
T50	2045	0	0	0
T51	2041	0	0	0
T57	1850	0	0	0
T227	0	2753	0	0
T231	0	5543	0	0
T232	0	2178	0	0
T233	0	3756	0	0
T234	0	6239	0	0
T235	0	3460	0	0
T236	0	3648	0	0
T237	0	3628	0	0
T238	0	6195	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216856779	75927	0	0
T14	3106	0	0	0
T17	1929	0	0	0
T21	297083	1748	0	0
T25	1797	0	0	0
T27	2258	0	0	0
T39	1947	0	0	0
T41	11873	0	0	0
T50	2045	0	0	0
T51	2041	0	0	0
T57	1850	0	0	0
T227	0	2537	0	0
T231	0	5195	0	0
T232	0	2156	0	0
T233	0	3798	0	0
T234	0	6051	0	0
T235	0	3153	0	0
T241	0	55	0	0
T242	0	4	0	0
T243	0	132	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216856779	68824	0	0
T14	3106	0	0	0
T17	1929	0	0	0
T21	297083	1652	0	0
T25	1797	0	0	0
T27	2258	0	0	0
T39	1947	0	0	0
T41	11873	0	0	0
T50	2045	0	0	0
T51	2041	0	0	0
T57	1850	0	0	0
T227	0	2234	0	0
T231	0	5048	0	0
T232	0	1984	0	0
T233	0	2910	0	0
T234	0	5409	0	0
T235	0	3211	0	0
T236	0	2962	0	0
T237	0	2914	0	0
T238	0	5353	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216856779	77886	0	0
T14	3106	0	0	0
T17	1929	0	0	0
T21	297083	1758	0	0
T25	1797	0	0	0
T27	2258	0	0	0
T39	1947	0	0	0
T41	11873	0	0	0
T50	2045	0	0	0
T51	2041	0	0	0
T57	1850	0	0	0
T227	0	2882	0	0
T231	0	5966	0	0
T232	0	2263	0	0
T233	0	3572	0	0
T234	0	5983	0	0
T235	0	3448	0	0
T236	0	3467	0	0
T237	0	3671	0	0
T238	0	6322	0	0