Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	79.67		66.67	100.00			72.34

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.76	98.25	93.31	90.85	87.79	95.50	96.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	87.19	99.92	92.06	47.04	87.79	97.42	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.77	95.02	97.16	99.53		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T19,T12,T26

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T6,T27,T7

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T28	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T11,T19	Yes	T5,T11,T19	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T5,T29,T30	Yes	T5,T29,T30	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T3,T28	Yes	T1,T3,T28	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T31,T32	Yes	T1,T31,T32	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T31,T32	Yes	T1,T31,T32	INPUT
edn_i[3].edn_req	Yes	Yes	T1,T31,T6	Yes	T1,T31,T6	INPUT
edn_i[4].edn_req	Yes	Yes	T1,T2,T33	Yes	T1,T2,T33	INPUT
edn_i[5].edn_req	Yes	Yes	T1,T31,T24	Yes	T1,T31,T24	INPUT
edn_i[6].edn_req	Yes	Yes	T1,T31,T32	Yes	T1,T31,T32	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T28	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T3,T28	Yes	T1,T3,T28	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T1,T31,T32	Yes	T1,T31,T32	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T31,T34,T35	Yes	T31,T21,T34	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T31,T32	Yes	T1,T31,T32	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T31,T32	Yes	T1,T31,T32	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T20,T36,T37	Yes	T1,T32,T38	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T31,T32	Yes	T1,T31,T32	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T1,T31,T19	Yes	T1,T31,T19	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T1,T24,T39	Yes	T1,T24,T38	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T1,T31,T19	Yes	T1,T31,T19	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T2,T33,T31	Yes	T1,T2,T33	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T2,T20,T34	Yes	T2,T33,T31	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T1,T2,T33	Yes	T1,T2,T33	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T1,T31,T24	Yes	T1,T31,T24	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T1,T24,T20	Yes	T1,T31,T24	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T1,T31,T24	Yes	T1,T31,T24	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T1,T31,T7	Yes	T1,T31,T7	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T7,T34,T39	Yes	T1,T32,T7	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T1,T31,T32	Yes	T1,T31,T32	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T5	Yes	T1,T2,T4	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T12,T26,T40	Yes	T12,T26,T40	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T41,T19,T12	Yes	T41,T19,T12	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T41,T6,T27	Yes	T41,T6,T27	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T41,T19,T12	Yes	T41,T19,T12	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T41,T6,T27	Yes	T41,T6,T27	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T5,T42	Yes	T4,T5,T42	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T27	Yes	T4,T5,T27	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	34	72.34
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	34	72.34

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	235601321	235496573	0	0
CsrngAppIfOut_A	235601321	235496573	0	0
FpvSecCmCntAlertCheck_A	235601321	44	0	0
FpvSecCmGenCmdFifoRptrCheck_A	235601321	0	0	0
FpvSecCmGenCmdFifoWptrCheck_A	235601321	0	0	0
FpvSecCmMainFsmCheck_A	235601321	0	0	0
FpvSecCmRegWeOnehotCheck_A	235601321	0	0	0
FpvSecCmResCmdFifoRptrCheck_A	235601321	0	0	0
FpvSecCmResCmdFifoWptrCheck_A	235601321	0	0	0
IntrEdnCmdReqDoneKnownO_A	235601321	235496573	0	0
TlAReadyKnownO_A	235601321	235496573	0	0
TlDValidKnownO_A	235601321	235496573	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	235601321	0	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	235601321	0	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	235601321	0	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	235601321	0	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	235601321	0	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	235601321	0	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	235601321	0	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	235601321	478283	0	312
gen_edn_if_asserts[0].EdnDataStable_A	235601321	71461	0	412
gen_edn_if_asserts[0].EdnEndPointOut_A	235601321	235496573	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	235601321	89063	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	235601321	478283	0	312
gen_edn_if_asserts[1].EdnDataStable_A	235601321	8696	0	147
gen_edn_if_asserts[1].EdnEndPointOut_A	235601321	235496573	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	235601321	89063	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	235601321	478283	0	312
gen_edn_if_asserts[2].EdnDataStable_A	235601321	4114	0	125
gen_edn_if_asserts[2].EdnEndPointOut_A	235601321	235496573	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	235601321	89063	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	235601321	478283	0	312
gen_edn_if_asserts[3].EdnDataStable_A	235601321	4533	0	123
gen_edn_if_asserts[3].EdnEndPointOut_A	235601321	235496573	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	235601321	89063	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	235601321	478283	0	312
gen_edn_if_asserts[4].EdnDataStable_A	235601321	51605	0	102
gen_edn_if_asserts[4].EdnEndPointOut_A	235601321	235496573	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	235601321	89063	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	235601321	478283	0	312
gen_edn_if_asserts[5].EdnDataStable_A	235601321	3650	0	97
gen_edn_if_asserts[5].EdnEndPointOut_A	235601321	235496573	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	235601321	89063	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	235601321	478283	0	312
gen_edn_if_asserts[6].EdnDataStable_A	235601321	2038	0	87
gen_edn_if_asserts[6].EdnEndPointOut_A	235601321	235496573	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	235601321	89063	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	44	0	0
T13	4168	0	0	0
T16	1163	1	0	0
T17	1564	1	0	0
T18	0	1	0	0
T23	1775	0	0	0
T30	235691	0	0	0
T40	2673	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	1348	0	0	0
T51	1539	0	0	0
T52	894	0	0	0
T53	3840	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	478283	0	312
T1	4449	98	0	0
T2	3859	16	0	0
T3	1725	15	0	0
T4	17135	731	0	0
T5	794438	978	0	2
T10	2304	1317	0	2
T11	6189	45	0	0
T21	0	0	0	2
T22	0	0	0	2
T28	2715	41	0	0
T29	0	0	0	2
T30	0	0	0	2
T33	1180	67	0	0
T41	1288	1205	0	2
T42	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	71461	0	412
T1	4449	42	0	1
T2	3859	0	0	0
T3	1725	3	0	1
T4	17135	6	0	0
T5	794438	114	0	0
T10	2304	4	0	0
T11	6189	1095	0	1
T12	0	4	0	1
T24	0	3	0	1
T28	2715	3	0	1
T31	0	3	0	1
T33	1180	0	0	0
T34	0	0	0	1
T41	1288	0	0	0
T56	0	0	0	1
T57	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	89063	0	0
T6	1221	671	0	0
T7	1946	769	0	0
T8	0	1159	0	0
T9	0	645	0	0
T12	2491	0	0	0
T16	0	604	0	0
T17	0	633	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	33	0	0
T32	1445	0	0	0
T36	0	7	0	0
T38	2096	0	0	0
T58	0	1157	0	0
T59	0	1126	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	478283	0	312
T1	4449	98	0	0
T2	3859	16	0	0
T3	1725	15	0	0
T4	17135	731	0	0
T5	794438	978	0	2
T10	2304	1317	0	2
T11	6189	45	0	0
T21	0	0	0	2
T22	0	0	0	2
T28	2715	41	0	0
T29	0	0	0	2
T30	0	0	0	2
T33	1180	67	0	0
T41	1288	1205	0	2
T42	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	8696	0	147
T1	4449	6	0	1
T2	3859	0	0	0
T3	1725	0	0	0
T4	17135	0	0	0
T5	794438	0	0	0
T10	2304	0	0	0
T11	6189	0	0	0
T13	0	14	0	1
T21	0	4	0	0
T26	0	4	0	1
T28	2715	0	0	0
T31	0	30	0	1
T32	0	3	0	1
T33	1180	0	0	0
T34	0	9	0	1
T35	0	33	0	1
T40	0	4	0	1
T41	1288	0	0	0
T60	0	4	0	1
T61	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	89063	0	0
T6	1221	671	0	0
T7	1946	769	0	0
T8	0	1159	0	0
T9	0	645	0	0
T12	2491	0	0	0
T16	0	604	0	0
T17	0	633	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	33	0	0
T32	1445	0	0	0
T36	0	7	0	0
T38	2096	0	0	0
T58	0	1157	0	0
T59	0	1126	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	478283	0	312
T1	4449	98	0	0
T2	3859	16	0	0
T3	1725	15	0	0
T4	17135	731	0	0
T5	794438	978	0	2
T10	2304	1317	0	2
T11	6189	45	0	0
T21	0	0	0	2
T22	0	0	0	2
T28	2715	41	0	0
T29	0	0	0	2
T30	0	0	0	2
T33	1180	67	0	0
T41	1288	1205	0	2
T42	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	4114	0	125
T1	4449	13	0	1
T2	3859	0	0	0
T3	1725	0	0	0
T4	17135	0	0	0
T5	794438	0	0	0
T10	2304	0	0	0
T11	6189	0	0	0
T13	0	3	0	1
T20	0	42	0	1
T28	2715	0	0	0
T31	0	3	0	1
T32	0	11	0	1
T33	1180	0	0	0
T34	0	3	0	1
T36	0	1	0	0
T38	0	3	0	1
T41	1288	0	0	0
T53	0	3	0	1
T62	0	4	0	1
T63	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	89063	0	0
T6	1221	671	0	0
T7	1946	769	0	0
T8	0	1159	0	0
T9	0	645	0	0
T12	2491	0	0	0
T16	0	604	0	0
T17	0	633	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	33	0	0
T32	1445	0	0	0
T36	0	7	0	0
T38	2096	0	0	0
T58	0	1157	0	0
T59	0	1126	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	478283	0	312
T1	4449	98	0	0
T2	3859	16	0	0
T3	1725	15	0	0
T4	17135	731	0	0
T5	794438	978	0	2
T10	2304	1317	0	2
T11	6189	45	0	0
T21	0	0	0	2
T22	0	0	0	2
T28	2715	41	0	0
T29	0	0	0	2
T30	0	0	0	2
T33	1180	67	0	0
T41	1288	1205	0	2
T42	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	4533	0	123
T1	4449	41	0	1
T2	3859	0	0	0
T3	1725	0	0	0
T4	17135	0	0	0
T5	794438	0	0	0
T10	2304	0	0	0
T11	6189	0	0	0
T13	0	3	0	1
T19	0	4	0	1
T24	0	58	0	1
T28	2715	0	0	0
T31	0	3	0	1
T32	0	3	0	1
T33	1180	0	0	0
T38	0	3	0	1
T39	0	44	0	1
T41	1288	0	0	0
T64	0	3	0	1
T65	0	3	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	89063	0	0
T6	1221	671	0	0
T7	1946	769	0	0
T8	0	1159	0	0
T9	0	645	0	0
T12	2491	0	0	0
T16	0	604	0	0
T17	0	633	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	33	0	0
T32	1445	0	0	0
T36	0	7	0	0
T38	2096	0	0	0
T58	0	1157	0	0
T59	0	1126	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	478283	0	312
T1	4449	98	0	0
T2	3859	16	0	0
T3	1725	15	0	0
T4	17135	731	0	0
T5	794438	978	0	2
T10	2304	1317	0	2
T11	6189	45	0	0
T21	0	0	0	2
T22	0	0	0	2
T28	2715	41	0	0
T29	0	0	0	2
T30	0	0	0	2
T33	1180	67	0	0
T41	1288	1205	0	2
T42	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	51605	0	102
T1	4449	3	0	1
T2	3859	33	0	1
T3	1725	0	0	0
T4	17135	0	0	0
T5	794438	0	0	0
T10	2304	0	0	0
T11	6189	0	0	0
T13	0	0	0	1
T20	0	633	0	1
T26	0	4	0	0
T28	2715	0	0	0
T31	0	3	0	1
T33	1180	3	0	1
T34	0	36	0	1
T39	0	3	0	1
T41	1288	0	0	0
T50	0	3	0	1
T59	0	1	0	0
T66	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	89063	0	0
T6	1221	671	0	0
T7	1946	769	0	0
T8	0	1159	0	0
T9	0	645	0	0
T12	2491	0	0	0
T16	0	604	0	0
T17	0	633	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	33	0	0
T32	1445	0	0	0
T36	0	7	0	0
T38	2096	0	0	0
T58	0	1157	0	0
T59	0	1126	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	478283	0	312
T1	4449	98	0	0
T2	3859	16	0	0
T3	1725	15	0	0
T4	17135	731	0	0
T5	794438	978	0	2
T10	2304	1317	0	2
T11	6189	45	0	0
T21	0	0	0	2
T22	0	0	0	2
T28	2715	41	0	0
T29	0	0	0	2
T30	0	0	0	2
T33	1180	67	0	0
T41	1288	1205	0	2
T42	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	3650	0	97
T1	4449	46	0	1
T2	3859	0	0	0
T3	1725	0	0	0
T4	17135	0	0	0
T5	794438	0	0	0
T10	2304	0	0	0
T11	6189	0	0	0
T13	0	3	0	1
T20	0	50	0	1
T24	0	444	0	1
T27	0	1	0	0
T28	2715	0	0	0
T31	0	3	0	1
T33	1180	0	0	0
T39	0	3	0	1
T41	1288	0	0	0
T53	0	3	0	1
T67	0	8	0	1
T68	0	3	0	1
T69	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	89063	0	0
T6	1221	671	0	0
T7	1946	769	0	0
T8	0	1159	0	0
T9	0	645	0	0
T12	2491	0	0	0
T16	0	604	0	0
T17	0	633	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	33	0	0
T32	1445	0	0	0
T36	0	7	0	0
T38	2096	0	0	0
T58	0	1157	0	0
T59	0	1126	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	478283	0	312
T1	4449	98	0	0
T2	3859	16	0	0
T3	1725	15	0	0
T4	17135	731	0	0
T5	794438	978	0	2
T10	2304	1317	0	2
T11	6189	45	0	0
T21	0	0	0	2
T22	0	0	0	2
T28	2715	41	0	0
T29	0	0	0	2
T30	0	0	0	2
T33	1180	67	0	0
T41	1288	1205	0	2
T42	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	2038	0	87
T1	4449	3	0	1
T2	3859	0	0	0
T3	1725	0	0	0
T4	17135	0	0	0
T5	794438	0	0	0
T10	2304	0	0	0
T11	6189	0	0	0
T20	0	3	0	1
T28	2715	0	0	0
T31	0	3	0	1
T32	0	3	0	1
T33	1180	0	0	0
T34	0	20	0	1
T39	0	53	0	1
T41	1288	0	0	0
T70	0	4	0	1
T71	0	4	0	1
T72	0	58	0	1
T73	0	3	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	235496573	0	0
T1	4449	4353	0	0
T2	3859	3768	0	0
T3	1725	1646	0	0
T4	17135	16596	0	0
T5	794438	794429	0	0
T10	2304	2234	0	0
T11	6189	6111	0	0
T28	2715	2621	0	0
T33	1180	1129	0	0
T41	1288	1207	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	235601321	89063	0	0
T6	1221	671	0	0
T7	1946	769	0	0
T8	0	1159	0	0
T9	0	645	0	0
T12	2491	0	0	0
T16	0	604	0	0
T17	0	633	0	0
T19	2004	0	0	0
T20	4983	0	0	0
T21	2143	0	0	0
T24	6339	0	0	0
T27	586	33	0	0
T32	1445	0	0	0
T36	0	7	0	0
T38	2096	0	0	0
T58	0	1157	0	0
T59	0	1126	0	0