Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.67		66.67	100.00			72.34	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	236123574	10710826	0	0
boot_gen_cmd_rd_A	236123574	36409	0	0
boot_ins_cmd_rd_A	236123574	40802	0	0
ctrl_rd_A	236123574	36263	0	0
err_code_test_rd_A	236123574	40781	0	0
intr_enable_rd_A	236123574	40886	0	0
max_num_reqs_between_reseeds_rd_A	236123574	37163	0	0
regwen_rd_A	236123574	42122	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236123574	10710826	0	0
T5	794438	449047	0	0
T6	1221	0	0	0
T10	2304	0	0	0
T11	6189	0	0	0
T12	2491	0	0	0
T19	2004	0	0	0
T29	0	81272	0	0
T30	0	87973	0	0
T31	3882	0	0	0
T32	1445	0	0	0
T33	1180	0	0	0
T41	1288	0	0	0
T135	0	260401	0	0
T228	0	321531	0	0
T229	0	63280	0	0
T230	0	120578	0	0
T231	0	257985	0	0
T232	0	55064	0	0
T233	0	103935	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236123574	36409	0	0
T30	235691	1307	0	0
T36	2052	0	0	0
T40	2673	0	0	0
T52	894	0	0	0
T53	3840	0	0	0
T61	2276	0	0	0
T70	2084	0	0	0
T133	24522	0	0	0
T232	0	1659	0	0
T234	0	1931	0	0
T235	0	2744	0	0
T236	0	1991	0	0
T237	0	984	0	0
T238	0	7728	0	0
T239	0	4214	0	0
T240	0	3261	0	0
T241	0	5357	0	0
T242	1691	0	0	0
T243	1092	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236123574	40802	0	0
T30	235691	1564	0	0
T36	2052	0	0	0
T40	2673	0	0	0
T52	894	0	0	0
T53	3840	0	0	0
T61	2276	0	0	0
T70	2084	0	0	0
T133	24522	0	0	0
T232	0	1761	0	0
T234	0	2188	0	0
T235	0	2964	0	0
T236	0	2223	0	0
T237	0	1048	0	0
T238	0	8900	0	0
T239	0	4734	0	0
T240	0	3567	0	0
T241	0	5688	0	0
T242	1691	0	0	0
T243	1092	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236123574	36263	0	0
T13	4168	0	0	0
T16	1163	0	0	0
T17	1564	0	0	0
T22	2930	4	0	0
T23	1775	0	0	0
T30	0	1382	0	0
T39	1844	0	0	0
T50	1348	0	0	0
T68	579	0	0	0
T138	0	2	0	0
T155	0	2	0	0
T232	0	1746	0	0
T234	0	1927	0	0
T244	0	2	0	0
T245	0	5	0	0
T246	0	7	0	0
T247	0	2	0	0
T248	1110	0	0	0
T249	2278	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236123574	40781	0	0
T30	235691	1718	0	0
T36	2052	0	0	0
T40	2673	0	0	0
T52	894	0	0	0
T53	3840	0	0	0
T61	2276	0	0	0
T70	2084	0	0	0
T133	24522	0	0	0
T232	0	1662	0	0
T234	0	2068	0	0
T235	0	3073	0	0
T236	0	2107	0	0
T237	0	1226	0	0
T238	0	9040	0	0
T239	0	4650	0	0
T240	0	3451	0	0
T241	0	5646	0	0
T242	1691	0	0	0
T243	1092	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236123574	40886	0	0
T16	1163	0	0	0
T22	2930	0	0	0
T29	204298	0	0	0
T30	0	1349	0	0
T39	1844	0	0	0
T50	1348	0	0	0
T67	1817	0	0	0
T68	579	0	0	0
T131	19830	61	0	0
T133	0	68	0	0
T232	0	2028	0	0
T234	0	2061	0	0
T244	0	78	0	0
T245	0	49	0	0
T246	0	16	0	0
T248	1110	0	0	0
T249	2278	0	0	0
T250	0	15	0	0
T251	0	46	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236123574	37163	0	0
T30	235691	1434	0	0
T36	2052	0	0	0
T40	2673	0	0	0
T52	894	0	0	0
T53	3840	0	0	0
T61	2276	0	0	0
T70	2084	0	0	0
T133	24522	0	0	0
T232	0	1533	0	0
T234	0	1853	0	0
T235	0	2576	0	0
T236	0	1889	0	0
T237	0	1118	0	0
T238	0	8111	0	0
T239	0	4030	0	0
T240	0	3130	0	0
T241	0	5146	0	0
T242	1691	0	0	0
T243	1092	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236123574	42122	0	0
T30	235691	1519	0	0
T36	2052	0	0	0
T40	2673	0	0	0
T52	894	0	0	0
T53	3840	0	0	0
T61	2276	0	0	0
T70	2084	0	0	0
T133	24522	0	0	0
T232	0	1720	0	0
T234	0	1985	0	0
T235	0	3046	0	0
T236	0	2289	0	0
T237	0	1076	0	0
T238	0	9080	0	0
T239	0	4675	0	0
T240	0	3843	0	0
T241	0	5726	0	0
T242	1691	0	0	0
T243	1092	0	0	0