Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	79.67		66.67	100.00			72.34

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.85	98.25	93.31	90.85	88.37	95.50	96.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	87.28	99.92	92.06	47.04	88.37	97.42	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.77	95.02	97.16	99.53		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T16,T20,T21

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T5

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T20,T22	Yes	T4,T20,T22	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T4,T16	Yes	T2,T4,T16	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T16	Yes	T1,T2,T16	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
edn_i[1].edn_req	Yes	Yes	T18,T26,T27	Yes	T18,T26,T27	INPUT
edn_i[2].edn_req	Yes	Yes	T20,T18,T27	Yes	T20,T18,T27	INPUT
edn_i[3].edn_req	Yes	Yes	T18,T28,T29	Yes	T18,T28,T29	INPUT
edn_i[4].edn_req	Yes	Yes	T21,T18,T19	Yes	T21,T18,T19	INPUT
edn_i[5].edn_req	Yes	Yes	T9,T21,T18	Yes	T9,T21,T18	INPUT
edn_i[6].edn_req	Yes	Yes	T28,T30,T31	Yes	T28,T30,T31	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T16,T8	Yes	T2,T16,T8	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T5,T32,T22	Yes	T2,T5,T8	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T16	Yes	T1,T2,T16	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T26,T27,T28	Yes	T18,T26,T27	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T26,T27,T28	Yes	T18,T26,T27	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T18,T26,T27	Yes	T18,T26,T27	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T18,T27,T33	Yes	T18,T27,T28	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T27,T30,T34	Yes	T20,T27,T35	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T20,T18,T27	Yes	T20,T18,T27	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T18,T28,T29	Yes	T18,T28,T29	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T36,T31,T11	Yes	T18,T28,T36	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T18,T28,T29	Yes	T18,T28,T29	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T21,T28,T37	Yes	T21,T18,T19	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T28,T38,T39	Yes	T18,T28,T38	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T21,T18,T19	Yes	T21,T18,T19	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T9,T21,T18	Yes	T9,T21,T18	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T9,T27,T40	Yes	T9,T27,T30	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T9,T21,T18	Yes	T9,T21,T18	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T28,T30,T31	Yes	T28,T30,T31	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T28,T30,T31	Yes	T28,T30,T31	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T28,T30,T31	Yes	T28,T30,T31	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T2,T32,T9	Yes	T2,T8,T9	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T32,T9,T22	Yes	T2,T8,T9	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T16	Yes	T1,T2,T16	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T20,T21,T41	Yes	T20,T21,T41	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T16,T20	Yes	T3,T16,T20	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T16,T20	Yes	T3,T16,T20	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T23,T42,T43	Yes	T23,T42,T43	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T44,T23	Yes	T1,T44,T23	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	34	72.34
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	34	72.34

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	232864084	232762796	0	0
CsrngAppIfOut_A	232864084	232762796	0	0
FpvSecCmCntAlertCheck_A	232864084	39	0	0
FpvSecCmGenCmdFifoRptrCheck_A	232864084	0	0	0
FpvSecCmGenCmdFifoWptrCheck_A	232864084	0	0	0
FpvSecCmMainFsmCheck_A	232864084	0	0	0
FpvSecCmRegWeOnehotCheck_A	232864084	0	0	0
FpvSecCmResCmdFifoRptrCheck_A	232864084	0	0	0
FpvSecCmResCmdFifoWptrCheck_A	232864084	0	0	0
IntrEdnCmdReqDoneKnownO_A	232864084	232762796	0	0
TlAReadyKnownO_A	232864084	232762796	0	0
TlDValidKnownO_A	232864084	232762796	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	232864084	0	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	232864084	0	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	232864084	0	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	232864084	0	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	232864084	0	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	232864084	0	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	232864084	0	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	232864084	458862	0	320
gen_edn_if_asserts[0].EdnDataStable_A	232864084	27671	0	407
gen_edn_if_asserts[0].EdnEndPointOut_A	232864084	232762796	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	232864084	87514	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	232864084	458862	0	320
gen_edn_if_asserts[1].EdnDataStable_A	232864084	4178	0	130
gen_edn_if_asserts[1].EdnEndPointOut_A	232864084	232762796	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	232864084	87514	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	232864084	458862	0	320
gen_edn_if_asserts[2].EdnDataStable_A	232864084	6182	0	119
gen_edn_if_asserts[2].EdnEndPointOut_A	232864084	232762796	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	232864084	87514	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	232864084	458862	0	320
gen_edn_if_asserts[3].EdnDataStable_A	232864084	4775	0	107
gen_edn_if_asserts[3].EdnEndPointOut_A	232864084	232762796	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	232864084	87514	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	232864084	458862	0	320
gen_edn_if_asserts[4].EdnDataStable_A	232864084	3675	0	88
gen_edn_if_asserts[4].EdnEndPointOut_A	232864084	232762796	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	232864084	87514	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	232864084	458862	0	320
gen_edn_if_asserts[5].EdnDataStable_A	232864084	53757	0	90
gen_edn_if_asserts[5].EdnEndPointOut_A	232864084	232762796	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	232864084	87514	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	232864084	458862	0	320
gen_edn_if_asserts[6].EdnDataStable_A	232864084	2524	0	66
gen_edn_if_asserts[6].EdnEndPointOut_A	232864084	232762796	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	232864084	87514	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	39	0	0
T13	1929	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T24	120018	0	0	0
T39	1788	0	0	0
T43	25470	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	1631	0	0	0
T54	872	0	0	0
T55	2182	0	0	0
T56	2804	0	0	0
T57	904	0	0	0
T58	930	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	458862	0	320
T1	670	188	0	0
T2	1979	31	0	0
T3	979	893	0	2
T4	970	506	0	0
T5	931	404	0	0
T8	2490	222	0	0
T16	2399	290	0	0
T19	0	0	0	2
T20	1629	129	0	0
T23	0	0	0	2
T32	1543	11	0	0
T45	498	161	0	0
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	27671	0	407
T1	670	1	0	0
T2	1979	16	0	1
T3	979	0	0	0
T4	970	0	0	0
T5	931	1	0	0
T8	2490	15	0	1
T16	2399	4	0	1
T17	0	0	0	1
T20	1629	0	0	0
T22	0	35	0	1
T32	1543	8	0	1
T44	0	1	0	0
T45	498	0	0	0
T66	0	3	0	1
T67	0	4	0	1
T68	0	0	0	1
T69	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	87514	0	0
T1	670	270	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	572	0	0
T5	931	362	0	0
T6	0	454	0	0
T8	2490	0	0	0
T13	0	1010	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	594	0	0
T44	0	1145	0	0
T45	498	244	0	0
T70	0	629	0	0
T71	0	1112	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	458862	0	320
T1	670	188	0	0
T2	1979	31	0	0
T3	979	893	0	2
T4	970	506	0	0
T5	931	404	0	0
T8	2490	222	0	0
T16	2399	290	0	0
T19	0	0	0	2
T20	1629	129	0	0
T23	0	0	0	2
T32	1543	11	0	0
T45	498	161	0	0
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	4178	0	130
T10	0	31	0	1
T18	5534	3	0	1
T19	3700	0	0	0
T26	2681	19	0	1
T27	2011	48	0	1
T28	2667	194	0	1
T30	0	3	0	1
T31	0	39	0	1
T33	987	0	0	0
T36	0	3	0	1
T72	0	4	0	1
T73	0	4	0	1
T74	1829	0	0	0
T75	1677	0	0	0
T76	2098	0	0	0
T77	3272	0	0	0

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	87514	0	0
T1	670	270	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	572	0	0
T5	931	362	0	0
T6	0	454	0	0
T8	2490	0	0	0
T13	0	1010	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	594	0	0
T44	0	1145	0	0
T45	498	244	0	0
T70	0	629	0	0
T71	0	1112	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	458862	0	320
T1	670	188	0	0
T2	1979	31	0	0
T3	979	893	0	2
T4	970	506	0	0
T5	931	404	0	0
T8	2490	222	0	0
T16	2399	290	0	0
T19	0	0	0	2
T20	1629	129	0	0
T23	0	0	0	2
T32	1543	11	0	0
T45	498	161	0	0
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	6182	0	119
T5	931	0	0	0
T8	2490	0	0	0
T9	7138	0	0	0
T18	0	3	0	1
T20	1629	4	0	1
T21	1833	0	0	0
T22	1292	0	0	0
T27	0	23	0	1
T28	0	3	0	1
T30	0	23	0	1
T32	1543	0	0	0
T33	0	3	0	1
T35	0	4	0	1
T37	0	4	0	1
T41	0	4	0	1
T44	2217	0	0	0
T45	498	0	0	0
T66	1488	0	0	0
T78	0	4	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	87514	0	0
T1	670	270	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	572	0	0
T5	931	362	0	0
T6	0	454	0	0
T8	2490	0	0	0
T13	0	1010	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	594	0	0
T44	0	1145	0	0
T45	498	244	0	0
T70	0	629	0	0
T71	0	1112	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	458862	0	320
T1	670	188	0	0
T2	1979	31	0	0
T3	979	893	0	2
T4	970	506	0	0
T5	931	404	0	0
T8	2490	222	0	0
T16	2399	290	0	0
T19	0	0	0	2
T20	1629	129	0	0
T23	0	0	0	2
T32	1543	11	0	0
T45	498	161	0	0
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	4775	0	107
T11	0	28	0	1
T18	5534	3	0	1
T19	3700	0	0	0
T26	2681	0	0	0
T27	2011	0	0	0
T28	2667	3	0	1
T29	0	4	0	1
T31	0	50	0	1
T33	987	0	0	0
T36	0	32	0	1
T39	0	3	0	1
T59	0	4	0	0
T74	1829	0	0	0
T75	1677	0	0	0
T76	2098	0	0	0
T77	3272	0	0	0
T79	0	4	0	0
T80	0	3	0	1
T81	0	0	0	1
T82	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	87514	0	0
T1	670	270	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	572	0	0
T5	931	362	0	0
T6	0	454	0	0
T8	2490	0	0	0
T13	0	1010	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	594	0	0
T44	0	1145	0	0
T45	498	244	0	0
T70	0	629	0	0
T71	0	1112	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	458862	0	320
T1	670	188	0	0
T2	1979	31	0	0
T3	979	893	0	2
T4	970	506	0	0
T5	931	404	0	0
T8	2490	222	0	0
T16	2399	290	0	0
T19	0	0	0	2
T20	1629	129	0	0
T23	0	0	0	2
T32	1543	11	0	0
T45	498	161	0	0
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	3675	0	88
T17	6478	0	0	0
T18	5534	3	0	1
T19	0	4	0	0
T21	1833	4	0	0
T26	2681	0	0	0
T27	2011	0	0	0
T28	0	40	0	1
T31	0	3	0	1
T37	0	4	0	0
T38	0	1	0	0
T39	0	48	0	1
T60	0	5	0	0
T67	2924	0	0	0
T68	1857	0	0	0
T69	2300	0	0	0
T74	1829	0	0	0
T75	1677	0	0	0
T80	0	3	0	1
T83	0	0	0	1
T84	0	0	0	1
T85	0	0	0	1
T86	0	0	0	1
T87	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	87514	0	0
T1	670	270	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	572	0	0
T5	931	362	0	0
T6	0	454	0	0
T8	2490	0	0	0
T13	0	1010	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	594	0	0
T44	0	1145	0	0
T45	498	244	0	0
T70	0	629	0	0
T71	0	1112	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	458862	0	320
T1	670	188	0	0
T2	1979	31	0	0
T3	979	893	0	2
T4	970	506	0	0
T5	931	404	0	0
T8	2490	222	0	0
T16	2399	290	0	0
T19	0	0	0	2
T20	1629	129	0	0
T23	0	0	0	2
T32	1543	11	0	0
T45	498	161	0	0
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	53757	0	90
T9	7138	1083	0	1
T11	0	3	0	1
T17	6478	0	0	0
T18	5534	3	0	1
T21	1833	4	0	1
T22	1292	0	0	0
T27	0	28	0	1
T30	0	3	0	1
T36	0	3	0	1
T39	0	3	0	1
T44	2217	0	0	0
T66	1488	0	0	0
T67	2924	0	0	0
T68	1857	0	0	0
T69	2300	0	0	0
T80	0	3	0	1
T88	0	4	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	87514	0	0
T1	670	270	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	572	0	0
T5	931	362	0	0
T6	0	454	0	0
T8	2490	0	0	0
T13	0	1010	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	594	0	0
T44	0	1145	0	0
T45	498	244	0	0
T70	0	629	0	0
T71	0	1112	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	458862	0	320
T1	670	188	0	0
T2	1979	31	0	0
T3	979	893	0	2
T4	970	506	0	0
T5	931	404	0	0
T8	2490	222	0	0
T16	2399	290	0	0
T19	0	0	0	2
T20	1629	129	0	0
T23	0	0	0	2
T32	1543	11	0	0
T45	498	161	0	0
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2
T63	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	2524	0	66
T11	0	3	0	1
T23	235967	0	0	0
T28	2667	27	0	1
T29	2502	0	0	0
T30	0	31	0	1
T31	0	33	0	1
T33	987	0	0	0
T35	2054	0	0	0
T39	0	7	0	1
T41	2471	0	0	0
T78	1894	0	0	0
T79	717	0	0	0
T80	0	795	0	1
T83	0	0	0	1
T86	0	0	0	1
T88	0	4	0	0
T89	0	1	0	0
T90	0	3	0	1
T91	0	4	0	0
T92	1677	0	0	0
T93	1766	0	0	0
T94	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	232762796	0	0
T1	670	513	0	0
T2	1979	1912	0	0
T3	979	895	0	0
T4	970	850	0	0
T5	931	751	0	0
T8	2490	2420	0	0
T16	2399	2338	0	0
T20	1629	1562	0	0
T32	1543	1474	0	0
T45	498	359	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232864084	87514	0	0
T1	670	270	0	0
T2	1979	0	0	0
T3	979	0	0	0
T4	970	572	0	0
T5	931	362	0	0
T6	0	454	0	0
T8	2490	0	0	0
T13	0	1010	0	0
T16	2399	0	0	0
T20	1629	0	0	0
T32	1543	0	0	0
T38	0	594	0	0
T44	0	1145	0	0
T45	498	244	0	0
T70	0	629	0	0
T71	0	1112	0	0