Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.67		66.67	100.00			72.34	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	233512860	10141209	0	0
boot_gen_cmd_rd_A	233512860	66084	0	0
boot_ins_cmd_rd_A	233512860	76880	0	0
ctrl_rd_A	233512860	65140	0	0
err_code_test_rd_A	233512860	77139	0	0
intr_enable_rd_A	233512860	74019	0	0
max_num_reqs_between_reseeds_rd_A	233512860	67848	0	0
regwen_rd_A	233512860	77814	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233512860	10141209	0	0
T23	235967	93113	0	0
T24	0	73413	0	0
T25	0	227343	0	0
T30	1462	0	0	0
T35	2054	0	0	0
T36	3461	0	0	0
T59	3060	0	0	0
T78	1894	0	0	0
T79	717	0	0	0
T93	1766	0	0	0
T157	0	391906	0	0
T163	1222	0	0	0
T243	0	66906	0	0
T244	0	91058	0	0
T245	0	375168	0	0
T246	0	223116	0	0
T247	0	349503	0	0
T248	0	73186	0	0
T249	2378	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233512860	66084	0	0
T7	2379	0	0	0
T25	657467	6802	0	0
T81	1568	0	0	0
T89	626	0	0	0
T156	2730	0	0	0
T157	950773	0	0	0
T226	2811	0	0	0
T243	0	1716	0	0
T244	0	1407	0	0
T245	0	10644	0	0
T246	0	6508	0	0
T250	0	3507	0	0
T251	0	1072	0	0
T252	0	3110	0	0
T253	0	3887	0	0
T254	0	7706	0	0
T255	798	0	0	0
T256	971	0	0	0
T257	1668	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233512860	76880	0	0
T7	2379	0	0	0
T25	657467	7410	0	0
T81	1568	0	0	0
T89	626	0	0	0
T156	2730	0	0	0
T157	950773	0	0	0
T226	2811	0	0	0
T243	0	2241	0	0
T244	0	1767	0	0
T245	0	12261	0	0
T246	0	7759	0	0
T250	0	4075	0	0
T251	0	1400	0	0
T252	0	3410	0	0
T253	0	4518	0	0
T254	0	9677	0	0
T255	798	0	0	0
T256	971	0	0	0
T257	1668	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233512860	65140	0	0
T6	1365	0	0	0
T25	0	6850	0	0
T31	2887	0	0	0
T37	2645	0	0	0
T38	1285	0	0	0
T48	0	8	0	0
T70	1332	0	0	0
T72	2339	0	0	0
T89	0	4	0	0
T95	1214	3	0	0
T115	950	0	0	0
T160	2288	0	0	0
T184	1655	0	0	0
T243	0	1879	0	0
T244	0	1283	0	0
T245	0	9952	0	0
T246	0	6627	0	0
T258	0	5	0	0
T259	0	6	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233512860	77139	0	0
T7	2379	0	0	0
T25	657467	8173	0	0
T81	1568	0	0	0
T89	626	0	0	0
T156	2730	0	0	0
T157	950773	0	0	0
T226	2811	0	0	0
T243	0	2053	0	0
T244	0	1628	0	0
T245	0	12470	0	0
T246	0	7832	0	0
T250	0	3945	0	0
T251	0	1185	0	0
T252	0	2984	0	0
T253	0	4470	0	0
T254	0	9644	0	0
T255	798	0	0	0
T256	971	0	0	0
T257	1668	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233512860	74019	0	0
T7	2379	0	0	0
T11	3299	0	0	0
T24	120018	0	0	0
T25	657467	7503	0	0
T39	1788	0	0	0
T43	25470	87	0	0
T55	2182	0	0	0
T56	2804	0	0	0
T57	904	0	0	0
T58	930	0	0	0
T243	0	2118	0	0
T244	0	1338	0	0
T245	0	10699	0	0
T246	0	7073	0	0
T259	0	8	0	0
T260	0	28	0	0
T261	0	13	0	0
T262	0	100	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233512860	67848	0	0
T7	2379	0	0	0
T25	657467	6897	0	0
T81	1568	0	0	0
T89	626	0	0	0
T156	2730	0	0	0
T157	950773	0	0	0
T226	2811	0	0	0
T243	0	2003	0	0
T244	0	1175	0	0
T245	0	10525	0	0
T246	0	7025	0	0
T250	0	3598	0	0
T251	0	1023	0	0
T252	0	2963	0	0
T253	0	3623	0	0
T254	0	7964	0	0
T255	798	0	0	0
T256	971	0	0	0
T257	1668	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233512860	77814	0	0
T7	2379	0	0	0
T25	657467	8004	0	0
T81	1568	0	0	0
T89	626	0	0	0
T156	2730	0	0	0
T157	950773	0	0	0
T226	2811	0	0	0
T243	0	2078	0	0
T244	0	1583	0	0
T245	0	11919	0	0
T246	0	7647	0	0
T250	0	4027	0	0
T251	0	1286	0	0
T252	0	3623	0	0
T253	0	4362	0	0
T254	0	9487	0	0
T255	798	0	0	0
T256	971	0	0	0
T257	1668	0	0	0