Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	79.67		66.67	100.00			72.34

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	98.25	93.25	90.85	87.21	95.50	96.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	87.07	99.92	91.98	47.04	87.21	97.42	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.77	95.02	97.16	99.53		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T9,T19

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T6,T13,T7

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T15,T19	Yes	T3,T15,T19	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T9	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T9	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
edn_i[1].edn_req	Yes	Yes	T3,T15,T23	Yes	T3,T15,T23	INPUT
edn_i[2].edn_req	Yes	Yes	T6,T24,T25	Yes	T6,T24,T25	INPUT
edn_i[3].edn_req	Yes	Yes	T3,T9,T16	Yes	T3,T9,T16	INPUT
edn_i[4].edn_req	Yes	Yes	T19,T16,T26	Yes	T19,T16,T26	INPUT
edn_i[5].edn_req	Yes	Yes	T1,T27,T28	Yes	T1,T27,T28	INPUT
edn_i[6].edn_req	Yes	Yes	T3,T29,T26	Yes	T3,T29,T26	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T3,T23,T28	Yes	T3,T15,T23	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T30,T31,T32	Yes	T3,T23,T33	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T3,T15,T23	Yes	T3,T15,T23	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T24,T25,T34	Yes	T24,T25,T34	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T35,T31,T36	Yes	T34,T37,T38	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T24,T25,T34	Yes	T24,T25,T34	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T9,T16,T24	Yes	T3,T9,T16	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T39,T28,T40	Yes	T16,T39,T28	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T3,T9,T16	Yes	T3,T9,T16	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T19,T16,T26	Yes	T19,T16,T26	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T16,T40,T33	Yes	T19,T16,T26	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T19,T16,T26	Yes	T19,T16,T26	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T1,T41,T42	Yes	T1,T27,T28	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T41,T40,T35	Yes	T1,T28,T41	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T1,T27,T28	Yes	T1,T27,T28	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T3,T29,T26	Yes	T3,T29,T26	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T29,T43,T40	Yes	T29,T43,T40	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T3,T29,T26	Yes	T3,T29,T26	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T2,T3,T44	Yes	T2,T3,T4	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T9,T23,T24	Yes	T9,T23,T24	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T9,T45	Yes	T1,T9,T45	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T6,T45,T13	Yes	T6,T45,T13	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T9,T45	Yes	T1,T9,T45	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T6,T45,T13	Yes	T6,T45,T13	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T5,T20	Yes	T4,T5,T20	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T20	Yes	T4,T5,T20	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	34	72.34
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	34	72.34

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	199715722	199611495	0	0
CsrngAppIfOut_A	199715722	199611495	0	0
FpvSecCmCntAlertCheck_A	199715722	35	0	0
FpvSecCmGenCmdFifoRptrCheck_A	199715722	0	0	0
FpvSecCmGenCmdFifoWptrCheck_A	199715722	0	0	0
FpvSecCmMainFsmCheck_A	199715722	0	0	0
FpvSecCmRegWeOnehotCheck_A	199715722	0	0	0
FpvSecCmResCmdFifoRptrCheck_A	199715722	0	0	0
FpvSecCmResCmdFifoWptrCheck_A	199715722	0	0	0
IntrEdnCmdReqDoneKnownO_A	199715722	199611495	0	0
TlAReadyKnownO_A	199715722	199611495	0	0
TlDValidKnownO_A	199715722	199611495	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	199715722	0	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	199715722	0	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	199715722	0	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	199715722	0	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	199715722	0	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	199715722	0	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	199715722	0	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	199715722	479959	0	300
gen_edn_if_asserts[0].EdnDataStable_A	199715722	24249	0	415
gen_edn_if_asserts[0].EdnEndPointOut_A	199715722	199611495	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	199715722	84190	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	199715722	479959	0	300
gen_edn_if_asserts[1].EdnDataStable_A	199715722	5577	0	129
gen_edn_if_asserts[1].EdnEndPointOut_A	199715722	199611495	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	199715722	84190	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	199715722	479959	0	300
gen_edn_if_asserts[2].EdnDataStable_A	199715722	5319	0	112
gen_edn_if_asserts[2].EdnEndPointOut_A	199715722	199611495	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	199715722	84190	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	199715722	479959	0	300
gen_edn_if_asserts[3].EdnDataStable_A	199715722	2923	0	103
gen_edn_if_asserts[3].EdnEndPointOut_A	199715722	199611495	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	199715722	84190	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	199715722	479959	0	300
gen_edn_if_asserts[4].EdnDataStable_A	199715722	7489	0	105
gen_edn_if_asserts[4].EdnEndPointOut_A	199715722	199611495	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	199715722	84190	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	199715722	479959	0	300
gen_edn_if_asserts[5].EdnDataStable_A	199715722	3230	0	76
gen_edn_if_asserts[5].EdnEndPointOut_A	199715722	199611495	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	199715722	84190	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	199715722	479959	0	300
gen_edn_if_asserts[6].EdnDataStable_A	199715722	1367	0	83
gen_edn_if_asserts[6].EdnEndPointOut_A	199715722	199611495	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	199715722	84190	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	199611495	0	0
T1	2135	2043	0	0
T2	7078	6991	0	0
T3	4116	4063	0	0
T4	9569	9207	0	0
T5	3034	2881	0	0
T6	747	618	0	0
T9	2381	2291	0	0
T10	3468	3391	0	0
T44	2893	2796	0	0
T45	1273	1203	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	199611495	0	0
T1	2135	2043	0	0
T2	7078	6991	0	0
T3	4116	4063	0	0
T4	9569	9207	0	0
T5	3034	2881	0	0
T6	747	618	0	0
T9	2381	2291	0	0
T10	3468	3391	0	0
T44	2893	2796	0	0
T45	1273	1203	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	35	0	0
T7	1138	1	0	0
T13	1163	1	0	0
T14	0	1	0	0
T16	2523	0	0	0
T17	2298	0	0	0
T23	1928	0	0	0
T24	1603	0	0	0
T29	3770	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	2192	0	0	0
T54	1433	0	0	0
T55	2436	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	199611495	0	0
T1	2135	2043	0	0
T2	7078	6991	0	0
T3	4116	4063	0	0
T4	9569	9207	0	0
T5	3034	2881	0	0
T6	747	618	0	0
T9	2381	2291	0	0
T10	3468	3391	0	0
T44	2893	2796	0	0
T45	1273	1203	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	199611495	0	0
T1	2135	2043	0	0
T2	7078	6991	0	0
T3	4116	4063	0	0
T4	9569	9207	0	0
T5	3034	2881	0	0
T6	747	618	0	0
T9	2381	2291	0	0
T10	3468	3391	0	0
T44	2893	2796	0	0
T45	1273	1203	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	199611495	0	0
T1	2135	2043	0	0
T2	7078	6991	0	0
T3	4116	4063	0	0
T4	9569	9207	0	0
T5	3034	2881	0	0
T6	747	618	0	0
T9	2381	2291	0	0
T10	3468	3391	0	0
T44	2893	2796	0	0
T45	1273	1203	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	479959	0	300
T1	2135	413	0	0
T2	7078	401	0	0
T3	4116	36	0	0
T4	9569	3142	0	2
T5	3034	1103	0	0
T6	747	348	0	0
T9	2381	259	0	0
T10	3468	189	0	0
T15	0	0	0	2
T20	0	0	0	2
T21	0	0	0	2
T25	0	0	0	2
T27	0	0	0	2
T44	2893	10	0	0
T45	1273	1201	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	24249	0	415
T2	7078	591	0	1
T3	4116	4	0	1
T4	9569	10	0	0
T5	3034	3	0	1
T6	747	0	0	0
T9	2381	0	0	0
T10	3468	44	0	1
T15	2886	0	0	0
T16	0	3	0	1
T17	0	0	0	1
T23	0	4	0	0
T44	2893	60	0	1
T45	1273	0	0	0
T53	0	4	0	1
T54	0	3	0	1
T55	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	199611495	0	0
T1	2135	2043	0	0
T2	7078	6991	0	0
T3	4116	4063	0	0
T4	9569	9207	0	0
T5	3034	2881	0	0
T6	747	618	0	0
T9	2381	2291	0	0
T10	3468	3391	0	0
T44	2893	2796	0	0
T45	1273	1203	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	84190	0	0
T6	747	312	0	0
T7	0	233	0	0
T8	0	1109	0	0
T10	3468	0	0	0
T13	1163	634	0	0
T14	0	1141	0	0
T15	2886	0	0	0
T16	2523	0	0	0
T19	2037	0	0	0
T23	1928	0	0	0
T43	0	20	0	0
T44	2893	0	0	0
T45	1273	0	0	0
T46	0	594	0	0
T53	2192	0	0	0
T59	0	299	0	0
T60	0	882	0	0
T61	0	7	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	479959	0	300
T1	2135	413	0	0
T2	7078	401	0	0
T3	4116	36	0	0
T4	9569	3142	0	2
T5	3034	1103	0	0
T6	747	348	0	0
T9	2381	259	0	0
T10	3468	189	0	0
T15	0	0	0	2
T20	0	0	0	2
T21	0	0	0	2
T25	0	0	0	2
T27	0	0	0	2
T44	2893	10	0	0
T45	1273	1201	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	5577	0	129
T3	4116	7	0	1
T4	9569	0	0	0
T5	3034	0	0	0
T6	747	0	0	0
T9	2381	0	0	0
T10	3468	0	0	0
T15	2886	4	0	0
T19	2037	0	0	0
T23	0	4	0	1
T28	0	3	0	1
T30	0	44	0	1
T33	0	3	0	1
T35	0	0	0	1
T44	2893	0	0	0
T45	1273	0	0	0
T62	0	3	0	1
T63	0	1	0	0
T64	0	4	0	1
T65	0	4	0	0
T66	0	0	0	1
T67	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	199611495	0	0
T1	2135	2043	0	0
T2	7078	6991	0	0
T3	4116	4063	0	0
T4	9569	9207	0	0
T5	3034	2881	0	0
T6	747	618	0	0
T9	2381	2291	0	0
T10	3468	3391	0	0
T44	2893	2796	0	0
T45	1273	1203	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	84190	0	0
T6	747	312	0	0
T7	0	233	0	0
T8	0	1109	0	0
T10	3468	0	0	0
T13	1163	634	0	0
T14	0	1141	0	0
T15	2886	0	0	0
T16	2523	0	0	0
T19	2037	0	0	0
T23	1928	0	0	0
T43	0	20	0	0
T44	2893	0	0	0
T45	1273	0	0	0
T46	0	594	0	0
T53	2192	0	0	0
T59	0	299	0	0
T60	0	882	0	0
T61	0	7	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	479959	0	300
T1	2135	413	0	0
T2	7078	401	0	0
T3	4116	36	0	0
T4	9569	3142	0	2
T5	3034	1103	0	0
T6	747	348	0	0
T9	2381	259	0	0
T10	3468	189	0	0
T15	0	0	0	2
T20	0	0	0	2
T21	0	0	0	2
T25	0	0	0	2
T27	0	0	0	2
T44	2893	10	0	0
T45	1273	1201	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	5319	0	112
T20	332453	0	0	0
T21	229113	0	0	0
T24	1603	4	0	1
T25	2283	4	0	0
T26	2736	0	0	0
T27	0	4	0	0
T29	3770	0	0	0
T33	0	0	0	1
T34	4354	11	0	1
T37	2021	4	0	1
T38	0	3	0	1
T39	0	3	0	1
T40	0	0	0	1
T41	0	3	0	1
T62	0	0	0	1
T68	0	7	0	1
T69	0	4	0	0
T70	1935	0	0	0
T71	5626	0	0	0

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	199611495	0	0
T1	2135	2043	0	0
T2	7078	6991	0	0
T3	4116	4063	0	0
T4	9569	9207	0	0
T5	3034	2881	0	0
T6	747	618	0	0
T9	2381	2291	0	0
T10	3468	3391	0	0
T44	2893	2796	0	0
T45	1273	1203	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	84190	0	0
T6	747	312	0	0
T7	0	233	0	0
T8	0	1109	0	0
T10	3468	0	0	0
T13	1163	634	0	0
T14	0	1141	0	0
T15	2886	0	0	0
T16	2523	0	0	0
T19	2037	0	0	0
T23	1928	0	0	0
T43	0	20	0	0
T44	2893	0	0	0
T45	1273	0	0	0
T46	0	594	0	0
T53	2192	0	0	0
T59	0	299	0	0
T60	0	882	0	0
T61	0	7	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	479959	0	300
T1	2135	413	0	0
T2	7078	401	0	0
T3	4116	36	0	0
T4	9569	3142	0	2
T5	3034	1103	0	0
T6	747	348	0	0
T9	2381	259	0	0
T10	3468	189	0	0
T15	0	0	0	2
T20	0	0	0	2
T21	0	0	0	2
T25	0	0	0	2
T27	0	0	0	2
T44	2893	10	0	0
T45	1273	1201	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	2923	0	103
T3	4116	3	0	1
T4	9569	0	0	0
T5	3034	0	0	0
T6	747	0	0	0
T9	2381	4	0	1
T10	3468	0	0	0
T15	2886	0	0	0
T16	0	3	0	1
T19	2037	0	0	0
T24	0	4	0	0
T28	0	17	0	1
T33	0	65	0	1
T39	0	49	0	1
T40	0	48	0	1
T41	0	3	0	1
T44	2893	0	0	0
T45	1273	0	0	0
T59	0	1	0	0
T62	0	0	0	1
T72	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	199611495	0	0
T1	2135	2043	0	0
T2	7078	6991	0	0
T3	4116	4063	0	0
T4	9569	9207	0	0
T5	3034	2881	0	0
T6	747	618	0	0
T9	2381	2291	0	0
T10	3468	3391	0	0
T44	2893	2796	0	0
T45	1273	1203	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	84190	0	0
T6	747	312	0	0
T7	0	233	0	0
T8	0	1109	0	0
T10	3468	0	0	0
T13	1163	634	0	0
T14	0	1141	0	0
T15	2886	0	0	0
T16	2523	0	0	0
T19	2037	0	0	0
T23	1928	0	0	0
T43	0	20	0	0
T44	2893	0	0	0
T45	1273	0	0	0
T46	0	594	0	0
T53	2192	0	0	0
T59	0	299	0	0
T60	0	882	0	0
T61	0	7	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	479959	0	300
T1	2135	413	0	0
T2	7078	401	0	0
T3	4116	36	0	0
T4	9569	3142	0	2
T5	3034	1103	0	0
T6	747	348	0	0
T9	2381	259	0	0
T10	3468	189	0	0
T15	0	0	0	2
T20	0	0	0	2
T21	0	0	0	2
T25	0	0	0	2
T27	0	0	0	2
T44	2893	10	0	0
T45	1273	1201	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	7489	0	105
T7	1138	0	0	0
T11	0	0	0	1
T13	1163	0	0	0
T16	2523	179	0	1
T17	2298	0	0	0
T19	2037	4	0	1
T23	1928	0	0	0
T24	1603	0	0	0
T26	0	4	0	1
T30	0	3	0	1
T33	0	25	0	1
T35	0	0	0	1
T40	0	19	0	1
T53	2192	0	0	0
T54	1433	0	0	0
T55	2436	0	0	0
T56	0	5	0	0
T62	0	15	0	1
T72	0	60	0	1
T73	0	4	0	0

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	199611495	0	0
T1	2135	2043	0	0
T2	7078	6991	0	0
T3	4116	4063	0	0
T4	9569	9207	0	0
T5	3034	2881	0	0
T6	747	618	0	0
T9	2381	2291	0	0
T10	3468	3391	0	0
T44	2893	2796	0	0
T45	1273	1203	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	84190	0	0
T6	747	312	0	0
T7	0	233	0	0
T8	0	1109	0	0
T10	3468	0	0	0
T13	1163	634	0	0
T14	0	1141	0	0
T15	2886	0	0	0
T16	2523	0	0	0
T19	2037	0	0	0
T23	1928	0	0	0
T43	0	20	0	0
T44	2893	0	0	0
T45	1273	0	0	0
T46	0	594	0	0
T53	2192	0	0	0
T59	0	299	0	0
T60	0	882	0	0
T61	0	7	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	479959	0	300
T1	2135	413	0	0
T2	7078	401	0	0
T3	4116	36	0	0
T4	9569	3142	0	2
T5	3034	1103	0	0
T6	747	348	0	0
T9	2381	259	0	0
T10	3468	189	0	0
T15	0	0	0	2
T20	0	0	0	2
T21	0	0	0	2
T25	0	0	0	2
T27	0	0	0	2
T44	2893	10	0	0
T45	1273	1201	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	3230	0	76
T1	2135	4	0	1
T2	7078	0	0	0
T3	4116	0	0	0
T4	9569	0	0	0
T5	3034	0	0	0
T6	747	0	0	0
T9	2381	0	0	0
T10	3468	0	0	0
T27	0	1	0	0
T28	0	3	0	1
T30	0	3	0	1
T33	0	3	0	1
T35	0	0	0	1
T40	0	19	0	1
T41	0	32	0	1
T42	0	4	0	1
T44	2893	0	0	0
T45	1273	0	0	0
T69	0	4	0	1
T74	0	4	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	199611495	0	0
T1	2135	2043	0	0
T2	7078	6991	0	0
T3	4116	4063	0	0
T4	9569	9207	0	0
T5	3034	2881	0	0
T6	747	618	0	0
T9	2381	2291	0	0
T10	3468	3391	0	0
T44	2893	2796	0	0
T45	1273	1203	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	84190	0	0
T6	747	312	0	0
T7	0	233	0	0
T8	0	1109	0	0
T10	3468	0	0	0
T13	1163	634	0	0
T14	0	1141	0	0
T15	2886	0	0	0
T16	2523	0	0	0
T19	2037	0	0	0
T23	1928	0	0	0
T43	0	20	0	0
T44	2893	0	0	0
T45	1273	0	0	0
T46	0	594	0	0
T53	2192	0	0	0
T59	0	299	0	0
T60	0	882	0	0
T61	0	7	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	479959	0	300
T1	2135	413	0	0
T2	7078	401	0	0
T3	4116	36	0	0
T4	9569	3142	0	2
T5	3034	1103	0	0
T6	747	348	0	0
T9	2381	259	0	0
T10	3468	189	0	0
T15	0	0	0	2
T20	0	0	0	2
T21	0	0	0	2
T25	0	0	0	2
T27	0	0	0	2
T44	2893	10	0	0
T45	1273	1201	0	2
T56	0	0	0	2
T57	0	0	0	2
T58	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	1367	0	83
T3	4116	3	0	1
T4	9569	0	0	0
T5	3034	0	0	0
T6	747	0	0	0
T9	2381	0	0	0
T10	3468	0	0	0
T15	2886	0	0	0
T19	2037	0	0	0
T26	0	4	0	0
T28	0	3	0	1
T29	0	70	0	1
T30	0	11	0	1
T31	0	0	0	1
T33	0	25	0	1
T35	0	3	0	1
T40	0	402	0	1
T41	0	3	0	1
T43	0	1	0	0
T44	2893	0	0	0
T45	1273	0	0	0
T75	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	199611495	0	0
T1	2135	2043	0	0
T2	7078	6991	0	0
T3	4116	4063	0	0
T4	9569	9207	0	0
T5	3034	2881	0	0
T6	747	618	0	0
T9	2381	2291	0	0
T10	3468	3391	0	0
T44	2893	2796	0	0
T45	1273	1203	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199715722	84190	0	0
T6	747	312	0	0
T7	0	233	0	0
T8	0	1109	0	0
T10	3468	0	0	0
T13	1163	634	0	0
T14	0	1141	0	0
T15	2886	0	0	0
T16	2523	0	0	0
T19	2037	0	0	0
T23	1928	0	0	0
T43	0	20	0	0
T44	2893	0	0	0
T45	1273	0	0	0
T46	0	594	0	0
T53	2192	0	0	0
T59	0	299	0	0
T60	0	882	0	0
T61	0	7	0	0