Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.67		66.67	100.00			72.34	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	200227144	8743476	0	0
boot_gen_cmd_rd_A	200227144	37174	0	0
boot_ins_cmd_rd_A	200227144	42512	0	0
ctrl_rd_A	200227144	36962	0	0
err_code_test_rd_A	200227144	43147	0	0
intr_enable_rd_A	200227144	43568	0	0
max_num_reqs_between_reseeds_rd_A	200227144	37904	0	0
regwen_rd_A	200227144	43882	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200227144	8743476	0	0
T20	332453	136162	0	0
T21	229113	132174	0	0
T22	0	104072	0	0
T25	2283	0	0	0
T26	2736	0	0	0
T34	4354	0	0	0
T37	2021	0	0	0
T38	1059	0	0	0
T57	0	373452	0	0
T58	0	117435	0	0
T70	1935	0	0	0
T71	5626	0	0	0
T95	0	129779	0	0
T220	0	302113	0	0
T221	0	96763	0	0
T222	0	395221	0	0
T223	0	27896	0	0
T224	1358	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200227144	37174	0	0
T49	1297	0	0	0
T80	594	0	0	0
T134	892	0	0	0
T195	2201	0	0	0
T197	1005	0	0	0
T222	108002	5773	0	0
T225	0	7584	0	0
T226	0	2916	0	0
T227	0	2282	0	0
T228	0	5764	0	0
T229	0	3592	0	0
T230	0	110	0	0
T231	0	2593	0	0
T232	0	2629	0	0
T233	0	3566	0	0
T234	2175	0	0	0
T235	2025	0	0	0
T236	2723	0	0	0
T237	1222	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200227144	42512	0	0
T49	1297	0	0	0
T80	594	0	0	0
T134	892	0	0	0
T195	2201	0	0	0
T197	1005	0	0	0
T222	108002	6517	0	0
T225	0	8316	0	0
T226	0	3646	0	0
T227	0	2284	0	0
T228	0	6659	0	0
T229	0	4158	0	0
T230	0	168	0	0
T231	0	3127	0	0
T232	0	2982	0	0
T233	0	4325	0	0
T234	2175	0	0	0
T235	2025	0	0	0
T236	2723	0	0	0
T237	1222	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200227144	36962	0	0
T14	0	10	0	0
T18	3416	0	0	0
T27	4154	0	0	0
T28	2006	0	0	0
T39	2209	0	0	0
T41	2676	5	0	0
T59	829	2	0	0
T65	0	2	0	0
T68	3686	0	0	0
T76	0	1	0	0
T96	22332	7	0	0
T100	1819	0	0	0
T111	0	3	0	0
T222	0	5820	0	0
T225	0	7457	0	0
T238	0	1	0	0
T239	2327	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200227144	43147	0	0
T49	1297	0	0	0
T80	594	0	0	0
T134	892	0	0	0
T195	2201	0	0	0
T197	1005	0	0	0
T222	108002	6881	0	0
T225	0	8617	0	0
T226	0	3528	0	0
T227	0	2329	0	0
T228	0	6847	0	0
T229	0	4105	0	0
T230	0	174	0	0
T231	0	3132	0	0
T232	0	2845	0	0
T233	0	4283	0	0
T234	2175	0	0	0
T235	2025	0	0	0
T236	2723	0	0	0
T237	1222	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200227144	43568	0	0
T18	3416	0	0	0
T21	229113	0	0	0
T22	252326	0	0	0
T37	2021	0	0	0
T38	1059	0	0	0
T43	1151	0	0	0
T71	5626	8	0	0
T96	22332	29	0	0
T97	925	0	0	0
T111	0	108	0	0
T222	0	6127	0	0
T224	1358	0	0	0
T225	0	8549	0	0
T226	0	3418	0	0
T227	0	2174	0	0
T228	0	6758	0	0
T229	0	3980	0	0
T240	0	58	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200227144	37904	0	0
T49	1297	0	0	0
T80	594	0	0	0
T134	892	0	0	0
T195	2201	0	0	0
T197	1005	0	0	0
T222	108002	5942	0	0
T225	0	7160	0	0
T226	0	3071	0	0
T227	0	1955	0	0
T228	0	5523	0	0
T229	0	3600	0	0
T230	0	177	0	0
T231	0	2628	0	0
T232	0	2679	0	0
T233	0	4021	0	0
T234	2175	0	0	0
T235	2025	0	0	0
T236	2723	0	0	0
T237	1222	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200227144	43882	0	0
T49	1297	0	0	0
T80	594	0	0	0
T134	892	0	0	0
T195	2201	0	0	0
T197	1005	0	0	0
T222	108002	6671	0	0
T225	0	8756	0	0
T226	0	3202	0	0
T227	0	2141	0	0
T228	0	6650	0	0
T229	0	4229	0	0
T230	0	182	0	0
T231	0	3175	0	0
T232	0	3086	0	0
T233	0	4432	0	0
T234	2175	0	0	0
T235	2025	0	0	0
T236	2723	0	0	0
T237	1222	0	0	0