Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	79.67		66.67	100.00			72.34

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.59	98.25	93.25	91.10	86.63	95.50	96.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	87.22	99.92	91.98	48.52	86.63	97.42	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.77	95.02	97.16	99.53		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T21

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T5

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T4,T9	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T9,T22	Yes	T2,T9,T22	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T9	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	INPUT
edn_i[1].edn_req	Yes	Yes	T4,T26,T27	Yes	T4,T26,T27	INPUT
edn_i[2].edn_req	Yes	Yes	T3,T28,T29	Yes	T3,T28,T29	INPUT
edn_i[3].edn_req	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
edn_i[4].edn_req	Yes	Yes	T14,T16,T33	Yes	T14,T16,T33	INPUT
edn_i[5].edn_req	Yes	Yes	T9,T34,T17	Yes	T9,T34,T17	INPUT
edn_i[6].edn_req	Yes	Yes	T35,T16,T36	Yes	T35,T16,T36	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T22,T10	Yes	T2,T22,T10	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T22,T10,T23	Yes	T2,T22,T10	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T2,T22,T10	Yes	T2,T22,T10	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T26,T27,T29	Yes	T26,T27,T29	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T29,T37,T32	Yes	T26,T27,T29	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T26,T27,T29	Yes	T26,T27,T29	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T3,T38,T30	Yes	T3,T29,T38	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T38,T32,T39	Yes	T38,T32,T40	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T3,T29,T38	Yes	T3,T29,T38	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T31,T32,T41	Yes	T30,T31,T32	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T16,T33,T29	Yes	T16,T33,T29	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T14,T29,T37	Yes	T14,T16,T29	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T14,T16,T33	Yes	T14,T16,T33	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T9,T34,T17	Yes	T9,T34,T17	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T34,T40,T41	Yes	T9,T34,T17	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T9,T34,T17	Yes	T9,T34,T17	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T35,T16,T36	Yes	T35,T16,T36	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T35,T16,T30	Yes	T35,T16,T17	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T35,T16,T36	Yes	T35,T16,T36	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T2,T9,T22	Yes	T9,T22,T34	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T9,T22,T34	Yes	T2,T22,T10	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T2,T3,T21	Yes	T2,T3,T21	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T3,T42	Yes	T2,T3,T42	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T3,T42	Yes	T2,T3,T42	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T14,T23,T24	Yes	T14,T23,T24	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	34	72.34
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	34	72.34

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	218283600	218180276	0	0
CsrngAppIfOut_A	218283600	218180276	0	0
FpvSecCmCntAlertCheck_A	218283600	47	0	0
FpvSecCmGenCmdFifoRptrCheck_A	218283600	0	0	0
FpvSecCmGenCmdFifoWptrCheck_A	218283600	0	0	0
FpvSecCmMainFsmCheck_A	218283600	0	0	0
FpvSecCmRegWeOnehotCheck_A	218283600	0	0	0
FpvSecCmResCmdFifoRptrCheck_A	218283600	0	0	0
FpvSecCmResCmdFifoWptrCheck_A	218283600	0	0	0
IntrEdnCmdReqDoneKnownO_A	218283600	218180276	0	0
TlAReadyKnownO_A	218283600	218180276	0	0
TlDValidKnownO_A	218283600	218180276	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	218283600	0	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	218283600	0	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	218283600	0	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	218283600	0	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	218283600	0	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	218283600	0	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	218283600	0	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	218283600	469110	0	302
gen_edn_if_asserts[0].EdnDataStable_A	218283600	22651	0	429
gen_edn_if_asserts[0].EdnEndPointOut_A	218283600	218180276	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	218283600	89639	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	218283600	469110	0	302
gen_edn_if_asserts[1].EdnDataStable_A	218283600	6151	0	141
gen_edn_if_asserts[1].EdnEndPointOut_A	218283600	218180276	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	218283600	89639	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	218283600	469110	0	302
gen_edn_if_asserts[2].EdnDataStable_A	218283600	3601	0	119
gen_edn_if_asserts[2].EdnEndPointOut_A	218283600	218180276	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	218283600	89639	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	218283600	469110	0	302
gen_edn_if_asserts[3].EdnDataStable_A	218283600	3896	0	112
gen_edn_if_asserts[3].EdnEndPointOut_A	218283600	218180276	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	218283600	89639	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	218283600	469110	0	302
gen_edn_if_asserts[4].EdnDataStable_A	218283600	4326	0	97
gen_edn_if_asserts[4].EdnEndPointOut_A	218283600	218180276	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	218283600	89639	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	218283600	469110	0	302
gen_edn_if_asserts[5].EdnDataStable_A	218283600	3109	0	96
gen_edn_if_asserts[5].EdnEndPointOut_A	218283600	218180276	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	218283600	89639	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	218283600	469110	0	302
gen_edn_if_asserts[6].EdnDataStable_A	218283600	2648	0	79
gen_edn_if_asserts[6].EdnEndPointOut_A	218283600	218180276	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	218283600	89639	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	218180276	0	0
T1	1873	1733	0	0
T2	2196	2140	0	0
T3	1903	1826	0	0
T4	1946	1764	0	0
T5	673	482	0	0
T9	4244	4168	0	0
T10	4603	4521	0	0
T22	2047	1956	0	0
T34	873	778	0	0
T42	1030	950	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	218180276	0	0
T1	1873	1733	0	0
T2	2196	2140	0	0
T3	1903	1826	0	0
T4	1946	1764	0	0
T5	673	482	0	0
T9	4244	4168	0	0
T10	4603	4521	0	0
T22	2047	1956	0	0
T34	873	778	0	0
T42	1030	950	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	47	0	0
T5	673	1	0	0
T10	4603	0	0	0
T14	2292	1	0	0
T15	0	1	0	0
T16	1732	0	0	0
T20	6346	0	0	0
T21	3156	0	0	0
T23	527574	0	0	0
T34	873	0	0	0
T35	3380	0	0	0
T42	1030	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	218180276	0	0
T1	1873	1733	0	0
T2	2196	2140	0	0
T3	1903	1826	0	0
T4	1946	1764	0	0
T5	673	482	0	0
T9	4244	4168	0	0
T10	4603	4521	0	0
T22	2047	1956	0	0
T34	873	778	0	0
T42	1030	950	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	218180276	0	0
T1	1873	1733	0	0
T2	2196	2140	0	0
T3	1903	1826	0	0
T4	1946	1764	0	0
T5	673	482	0	0
T9	4244	4168	0	0
T10	4603	4521	0	0
T22	2047	1956	0	0
T34	873	778	0	0
T42	1030	950	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	218180276	0	0
T1	1873	1733	0	0
T2	2196	2140	0	0
T3	1903	1826	0	0
T4	1946	1764	0	0
T5	673	482	0	0
T9	4244	4168	0	0
T10	4603	4521	0	0
T22	2047	1956	0	0
T34	873	778	0	0
T42	1030	950	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	469110	0	302
T1	1873	1095	0	0
T2	2196	270	0	0
T3	1903	249	0	0
T4	1946	1081	0	0
T5	673	254	0	0
T9	4244	1574	0	2
T10	4603	279	0	0
T17	0	0	0	2
T18	0	0	0	2
T22	2047	67	0	0
T23	0	0	0	2
T25	0	0	0	2
T34	873	68	0	0
T42	1030	948	0	2
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	22651	0	429
T2	2196	4	0	1
T3	1903	0	0	0
T4	1946	0	0	0
T5	673	0	0	0
T9	4244	0	0	0
T10	4603	723	0	1
T14	2292	0	0	0
T18	0	4	0	0
T19	0	0	0	1
T20	0	939	0	1
T21	0	4	0	1
T22	2047	19	0	1
T23	0	56	0	0
T34	873	0	0	0
T42	1030	0	0	0
T54	0	4	0	1
T55	0	3	0	1
T56	0	3	0	1
T57	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	218180276	0	0
T1	1873	1733	0	0
T2	2196	2140	0	0
T3	1903	1826	0	0
T4	1946	1764	0	0
T5	673	482	0	0
T9	4244	4168	0	0
T10	4603	4521	0	0
T22	2047	1956	0	0
T34	873	778	0	0
T42	1030	950	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	89639	0	0
T1	1873	1136	0	0
T2	2196	0	0	0
T3	1903	0	0	0
T4	1946	1173	0	0
T5	673	334	0	0
T6	0	640	0	0
T7	0	623	0	0
T9	4244	0	0	0
T10	4603	0	0	0
T14	0	1161	0	0
T15	0	387	0	0
T22	2047	0	0	0
T28	0	1112	0	0
T34	873	0	0	0
T42	1030	0	0	0
T58	0	361	0	0
T59	0	360	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	469110	0	302
T1	1873	1095	0	0
T2	2196	270	0	0
T3	1903	249	0	0
T4	1946	1081	0	0
T5	673	254	0	0
T9	4244	1574	0	2
T10	4603	279	0	0
T17	0	0	0	2
T18	0	0	0	2
T22	2047	67	0	0
T23	0	0	0	2
T25	0	0	0	2
T34	873	68	0	0
T42	1030	948	0	2
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	6151	0	141
T17	1886	0	0	0
T18	2379	0	0	0
T26	2404	4	0	1
T27	2019	4	0	1
T29	0	33	0	1
T30	0	3	0	1
T32	0	37	0	1
T36	2138	0	0	0
T37	0	351	0	1
T40	0	3	0	1
T41	0	26	0	1
T54	2104	0	0	0
T55	958	0	0	0
T56	1613	0	0	0
T57	2897	0	0	0
T58	776	0	0	0
T60	0	3	0	1
T61	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	218180276	0	0
T1	1873	1733	0	0
T2	2196	2140	0	0
T3	1903	1826	0	0
T4	1946	1764	0	0
T5	673	482	0	0
T9	4244	4168	0	0
T10	4603	4521	0	0
T22	2047	1956	0	0
T34	873	778	0	0
T42	1030	950	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	89639	0	0
T1	1873	1136	0	0
T2	2196	0	0	0
T3	1903	0	0	0
T4	1946	1173	0	0
T5	673	334	0	0
T6	0	640	0	0
T7	0	623	0	0
T9	4244	0	0	0
T10	4603	0	0	0
T14	0	1161	0	0
T15	0	387	0	0
T22	2047	0	0	0
T28	0	1112	0	0
T34	873	0	0	0
T42	1030	0	0	0
T58	0	361	0	0
T59	0	360	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	469110	0	302
T1	1873	1095	0	0
T2	2196	270	0	0
T3	1903	249	0	0
T4	1946	1081	0	0
T5	673	254	0	0
T9	4244	1574	0	2
T10	4603	279	0	0
T17	0	0	0	2
T18	0	0	0	2
T22	2047	67	0	0
T23	0	0	0	2
T25	0	0	0	2
T34	873	68	0	0
T42	1030	948	0	2
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	3601	0	119
T3	1903	4	0	1
T4	1946	0	0	0
T5	673	0	0	0
T9	4244	0	0	0
T10	4603	0	0	0
T14	2292	0	0	0
T22	2047	0	0	0
T29	0	3	0	1
T30	0	3	0	1
T32	0	11	0	1
T34	873	0	0	0
T35	3380	0	0	0
T37	0	3	0	1
T38	0	8	0	1
T40	0	3	0	1
T41	0	0	0	1
T42	1030	0	0	0
T52	0	4	0	0
T62	0	4	0	1
T63	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	218180276	0	0
T1	1873	1733	0	0
T2	2196	2140	0	0
T3	1903	1826	0	0
T4	1946	1764	0	0
T5	673	482	0	0
T9	4244	4168	0	0
T10	4603	4521	0	0
T22	2047	1956	0	0
T34	873	778	0	0
T42	1030	950	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	89639	0	0
T1	1873	1136	0	0
T2	2196	0	0	0
T3	1903	0	0	0
T4	1946	1173	0	0
T5	673	334	0	0
T6	0	640	0	0
T7	0	623	0	0
T9	4244	0	0	0
T10	4603	0	0	0
T14	0	1161	0	0
T15	0	387	0	0
T22	2047	0	0	0
T28	0	1112	0	0
T34	873	0	0	0
T42	1030	0	0	0
T58	0	361	0	0
T59	0	360	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	469110	0	302
T1	1873	1095	0	0
T2	2196	270	0	0
T3	1903	249	0	0
T4	1946	1081	0	0
T5	673	254	0	0
T9	4244	1574	0	2
T10	4603	279	0	0
T17	0	0	0	2
T18	0	0	0	2
T22	2047	67	0	0
T23	0	0	0	2
T25	0	0	0	2
T34	873	68	0	0
T42	1030	948	0	2
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	3896	0	112
T30	5495	3	0	1
T31	0	59	0	1
T32	0	60	0	1
T37	3500	0	0	0
T40	0	3	0	1
T41	0	881	0	1
T52	3804	0	0	0
T53	2504	0	0	0
T60	0	3	0	1
T61	0	3	0	1
T62	1851	0	0	0
T63	1904	0	0	0
T64	0	4	0	1
T65	0	3	0	1
T66	0	3	0	1
T67	24007	0	0	0
T68	4123	0	0	0
T69	508390	0	0	0
T70	6131	0	0	0

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	218180276	0	0
T1	1873	1733	0	0
T2	2196	2140	0	0
T3	1903	1826	0	0
T4	1946	1764	0	0
T5	673	482	0	0
T9	4244	4168	0	0
T10	4603	4521	0	0
T22	2047	1956	0	0
T34	873	778	0	0
T42	1030	950	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	89639	0	0
T1	1873	1136	0	0
T2	2196	0	0	0
T3	1903	0	0	0
T4	1946	1173	0	0
T5	673	334	0	0
T6	0	640	0	0
T7	0	623	0	0
T9	4244	0	0	0
T10	4603	0	0	0
T14	0	1161	0	0
T15	0	387	0	0
T22	2047	0	0	0
T28	0	1112	0	0
T34	873	0	0	0
T42	1030	0	0	0
T58	0	361	0	0
T59	0	360	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	469110	0	302
T1	1873	1095	0	0
T2	2196	270	0	0
T3	1903	249	0	0
T4	1946	1081	0	0
T5	673	254	0	0
T9	4244	1574	0	2
T10	4603	279	0	0
T17	0	0	0	2
T18	0	0	0	2
T22	2047	67	0	0
T23	0	0	0	2
T25	0	0	0	2
T34	873	68	0	0
T42	1030	948	0	2
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	4326	0	97
T14	2292	1	0	0
T16	1732	3	0	1
T17	1886	0	0	0
T20	6346	0	0	0
T21	3156	0	0	0
T23	527574	0	0	0
T26	2404	0	0	0
T29	0	23	0	1
T32	0	3	0	1
T33	0	4	0	1
T35	3380	0	0	0
T36	2138	0	0	0
T37	0	45	0	1
T40	0	29	0	1
T41	0	3	0	1
T53	0	4	0	0
T54	2104	0	0	0
T60	0	0	0	1
T71	0	3	0	1
T72	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	218180276	0	0
T1	1873	1733	0	0
T2	2196	2140	0	0
T3	1903	1826	0	0
T4	1946	1764	0	0
T5	673	482	0	0
T9	4244	4168	0	0
T10	4603	4521	0	0
T22	2047	1956	0	0
T34	873	778	0	0
T42	1030	950	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	89639	0	0
T1	1873	1136	0	0
T2	2196	0	0	0
T3	1903	0	0	0
T4	1946	1173	0	0
T5	673	334	0	0
T6	0	640	0	0
T7	0	623	0	0
T9	4244	0	0	0
T10	4603	0	0	0
T14	0	1161	0	0
T15	0	387	0	0
T22	2047	0	0	0
T28	0	1112	0	0
T34	873	0	0	0
T42	1030	0	0	0
T58	0	361	0	0
T59	0	360	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	469110	0	302
T1	1873	1095	0	0
T2	2196	270	0	0
T3	1903	249	0	0
T4	1946	1081	0	0
T5	673	254	0	0
T9	4244	1574	0	2
T10	4603	279	0	0
T17	0	0	0	2
T18	0	0	0	2
T22	2047	67	0	0
T23	0	0	0	2
T25	0	0	0	2
T34	873	68	0	0
T42	1030	948	0	2
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	3109	0	96
T5	673	0	0	0
T9	4244	4	0	0
T10	4603	0	0	0
T14	2292	0	0	0
T16	1732	0	0	0
T17	0	4	0	0
T21	3156	0	0	0
T22	2047	0	0	0
T29	0	3	0	1
T34	873	4	0	0
T35	3380	0	0	0
T40	0	35	0	1
T41	0	26	0	1
T42	1030	0	0	0
T60	0	16	0	1
T61	0	51	0	1
T73	0	3	0	1
T74	0	3	0	1
T75	0	0	0	1
T76	0	0	0	1
T77	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	218180276	0	0
T1	1873	1733	0	0
T2	2196	2140	0	0
T3	1903	1826	0	0
T4	1946	1764	0	0
T5	673	482	0	0
T9	4244	4168	0	0
T10	4603	4521	0	0
T22	2047	1956	0	0
T34	873	778	0	0
T42	1030	950	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	89639	0	0
T1	1873	1136	0	0
T2	2196	0	0	0
T3	1903	0	0	0
T4	1946	1173	0	0
T5	673	334	0	0
T6	0	640	0	0
T7	0	623	0	0
T9	4244	0	0	0
T10	4603	0	0	0
T14	0	1161	0	0
T15	0	387	0	0
T22	2047	0	0	0
T28	0	1112	0	0
T34	873	0	0	0
T42	1030	0	0	0
T58	0	361	0	0
T59	0	360	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	469110	0	302
T1	1873	1095	0	0
T2	2196	270	0	0
T3	1903	249	0	0
T4	1946	1081	0	0
T5	673	254	0	0
T9	4244	1574	0	2
T10	4603	279	0	0
T17	0	0	0	2
T18	0	0	0	2
T22	2047	67	0	0
T23	0	0	0	2
T25	0	0	0	2
T34	873	68	0	0
T42	1030	948	0	2
T50	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T53	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	2648	0	79
T16	1732	15	0	1
T17	1886	1	0	0
T18	0	1	0	0
T20	6346	0	0	0
T21	3156	0	0	0
T23	527574	0	0	0
T26	2404	0	0	0
T30	0	684	0	1
T35	3380	15	0	1
T36	2138	4	0	1
T37	0	3	0	1
T40	0	59	0	1
T54	2104	0	0	0
T58	776	0	0	0
T61	0	0	0	1
T66	0	0	0	1
T74	0	0	0	1
T78	0	4	0	0
T79	0	4	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	218180276	0	0
T1	1873	1733	0	0
T2	2196	2140	0	0
T3	1903	1826	0	0
T4	1946	1764	0	0
T5	673	482	0	0
T9	4244	4168	0	0
T10	4603	4521	0	0
T22	2047	1956	0	0
T34	873	778	0	0
T42	1030	950	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218283600	89639	0	0
T1	1873	1136	0	0
T2	2196	0	0	0
T3	1903	0	0	0
T4	1946	1173	0	0
T5	673	334	0	0
T6	0	640	0	0
T7	0	623	0	0
T9	4244	0	0	0
T10	4603	0	0	0
T14	0	1161	0	0
T15	0	387	0	0
T22	2047	0	0	0
T28	0	1112	0	0
T34	873	0	0	0
T42	1030	0	0	0
T58	0	361	0	0
T59	0	360	0	0