Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.67		66.67	100.00			72.34	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	218764711	9816147	0	0
boot_gen_cmd_rd_A	218764711	44258	0	0
boot_ins_cmd_rd_A	218764711	50622	0	0
ctrl_rd_A	218764711	44291	0	0
err_code_test_rd_A	218764711	50955	0	0
intr_enable_rd_A	218764711	50129	0	0
max_num_reqs_between_reseeds_rd_A	218764711	45642	0	0
regwen_rd_A	218764711	51096	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218764711	9816147	0	0
T17	1886	0	0	0
T18	2379	0	0	0
T20	6346	0	0	0
T23	527574	218585	0	0
T24	0	163714	0	0
T25	0	107950	0	0
T26	2404	0	0	0
T27	2019	0	0	0
T36	2138	0	0	0
T54	2104	0	0	0
T55	958	0	0	0
T58	776	0	0	0
T69	0	286932	0	0
T138	0	352548	0	0
T225	0	382975	0	0
T226	0	199100	0	0
T227	0	63884	0	0
T228	0	137756	0	0
T229	0	220654	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218764711	44258	0	0
T176	2657	0	0	0
T230	178062	2048	0	0
T231	785063	4597	0	0
T232	0	3016	0	0
T233	0	2591	0	0
T234	0	3803	0	0
T235	0	4217	0	0
T236	0	7298	0	0
T237	0	4408	0	0
T238	0	1496	0	0
T239	0	2730	0	0
T240	1039	0	0	0
T241	2855	0	0	0
T242	917	0	0	0
T243	2536	0	0	0
T244	1758	0	0	0
T245	1607	0	0	0
T246	1378	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218764711	50622	0	0
T176	2657	0	0	0
T230	178062	2246	0	0
T231	785063	4773	0	0
T232	0	3612	0	0
T233	0	2951	0	0
T234	0	4389	0	0
T235	0	5053	0	0
T236	0	8559	0	0
T237	0	4687	0	0
T238	0	1791	0	0
T239	0	3199	0	0
T240	1039	0	0	0
T241	2855	0	0	0
T242	917	0	0	0
T243	2536	0	0	0
T244	1758	0	0	0
T245	1607	0	0	0
T246	1378	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218764711	44291	0	0
T5	673	0	0	0
T9	4244	6	0	0
T10	4603	0	0	0
T14	2292	0	0	0
T16	1732	0	0	0
T21	3156	0	0	0
T22	2047	0	0	0
T34	873	0	0	0
T35	3380	0	0	0
T42	1030	0	0	0
T54	0	3	0	0
T230	0	1774	0	0
T231	0	4425	0	0
T232	0	2923	0	0
T233	0	2712	0	0
T244	0	2	0	0
T247	0	6	0	0
T248	0	3	0	0
T249	0	7	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218764711	50955	0	0
T176	2657	0	0	0
T230	178062	2020	0	0
T231	785063	5206	0	0
T232	0	3191	0	0
T233	0	2968	0	0
T234	0	4292	0	0
T235	0	5093	0	0
T236	0	8943	0	0
T237	0	5015	0	0
T238	0	1812	0	0
T239	0	3046	0	0
T240	1039	0	0	0
T241	2855	0	0	0
T242	917	0	0	0
T243	2536	0	0	0
T244	1758	0	0	0
T245	1607	0	0	0
T246	1378	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218764711	50129	0	0
T176	2657	0	0	0
T230	178062	1900	0	0
T231	785063	4627	0	0
T232	0	3367	0	0
T233	0	2878	0	0
T240	1039	0	0	0
T241	2855	0	0	0
T242	917	0	0	0
T243	2536	0	0	0
T244	1758	0	0	0
T245	1607	0	0	0
T246	1378	0	0	0
T247	0	36	0	0
T248	0	96	0	0
T250	0	17	0	0
T251	0	78	0	0
T252	0	74	0	0
T253	0	8	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218764711	45642	0	0
T176	2657	0	0	0
T230	178062	1827	0	0
T231	785063	4592	0	0
T232	0	3153	0	0
T233	0	2903	0	0
T234	0	3720	0	0
T235	0	4404	0	0
T236	0	7745	0	0
T237	0	4378	0	0
T238	0	1472	0	0
T239	0	2772	0	0
T240	1039	0	0	0
T241	2855	0	0	0
T242	917	0	0	0
T243	2536	0	0	0
T244	1758	0	0	0
T245	1607	0	0	0
T246	1378	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218764711	51096	0	0
T176	2657	0	0	0
T230	178062	2110	0	0
T231	785063	5492	0	0
T232	0	3424	0	0
T233	0	2933	0	0
T234	0	4177	0	0
T235	0	5025	0	0
T236	0	9017	0	0
T237	0	4693	0	0
T238	0	1560	0	0
T239	0	3361	0	0
T240	1039	0	0	0
T241	2855	0	0	0
T242	917	0	0	0
T243	2536	0	0	0
T244	1758	0	0	0
T245	1607	0	0	0
T246	1378	0	0	0