Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	79.67		66.67	100.00			72.34

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.94	98.25	93.25	90.85	88.95	95.50	96.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	87.37	99.92	91.98	47.04	88.95	97.42	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.77	95.02	97.16	99.53		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T21,T8

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T5,T22

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T21	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T8,T23	Yes	T2,T8,T23	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T27,T10,T4	Yes	T27,T10,T4	INPUT
edn_i[2].edn_req	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
edn_i[3].edn_req	Yes	Yes	T2,T27,T28	Yes	T2,T27,T28	INPUT
edn_i[4].edn_req	Yes	Yes	T27,T31,T32	Yes	T27,T31,T32	INPUT
edn_i[5].edn_req	Yes	Yes	T27,T30,T17	Yes	T27,T30,T17	INPUT
edn_i[6].edn_req	Yes	Yes	T10,T33,T32	Yes	T10,T33,T32	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T27,T10,T34	Yes	T27,T10,T34	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T27,T4,T34	Yes	T27,T10,T4	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T27,T10,T4	Yes	T27,T10,T4	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T28,T31,T35	Yes	T28,T29,T34	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T2,T27,T28	Yes	T2,T27,T28	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T36,T37,T38	Yes	T2,T27,T39	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T2,T27,T28	Yes	T2,T27,T28	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T27,T31,T32	Yes	T27,T31,T32	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T27,T32,T40	Yes	T27,T32,T40	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T27,T31,T32	Yes	T27,T31,T32	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T30,T17,T33	Yes	T27,T30,T17	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T30,T33,T20	Yes	T30,T17,T33	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T27,T30,T17	Yes	T27,T30,T17	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T33,T32,T41	Yes	T10,T33,T32	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T33,T38,T42	Yes	T33,T32,T38	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T10,T33,T32	Yes	T10,T33,T32	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T2,T3,T21	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T43,T27,T9	Yes	T3,T27,T9	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T8,T27	Yes	T3,T43,T27	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T8,T16,T44	Yes	T8,T16,T44	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T21,T8	Yes	T2,T21,T8	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T23,T4,T5	Yes	T23,T4,T5	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T21,T8	Yes	T2,T21,T8	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T23,T4,T5	Yes	T23,T4,T5	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	34	72.34
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	34	72.34

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	211061742	210956477	0	0
CsrngAppIfOut_A	211061742	210956477	0	0
FpvSecCmCntAlertCheck_A	211061742	38	0	0
FpvSecCmGenCmdFifoRptrCheck_A	211061742	0	0	0
FpvSecCmGenCmdFifoWptrCheck_A	211061742	0	0	0
FpvSecCmMainFsmCheck_A	211061742	0	0	0
FpvSecCmRegWeOnehotCheck_A	211061742	0	0	0
FpvSecCmResCmdFifoRptrCheck_A	211061742	0	0	0
FpvSecCmResCmdFifoWptrCheck_A	211061742	0	0	0
IntrEdnCmdReqDoneKnownO_A	211061742	210956477	0	0
TlAReadyKnownO_A	211061742	210956477	0	0
TlDValidKnownO_A	211061742	210956477	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	211061742	0	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	211061742	0	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	211061742	0	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	211061742	0	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	211061742	0	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	211061742	0	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	211061742	0	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	211061742	525952	0	302
gen_edn_if_asserts[0].EdnDataStable_A	211061742	78197	0	420
gen_edn_if_asserts[0].EdnEndPointOut_A	211061742	210956477	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	211061742	90681	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	211061742	525952	0	302
gen_edn_if_asserts[1].EdnDataStable_A	211061742	5606	0	148
gen_edn_if_asserts[1].EdnEndPointOut_A	211061742	210956477	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	211061742	90681	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	211061742	525952	0	302
gen_edn_if_asserts[2].EdnDataStable_A	211061742	6130	0	127
gen_edn_if_asserts[2].EdnEndPointOut_A	211061742	210956477	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	211061742	90681	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	211061742	525952	0	302
gen_edn_if_asserts[3].EdnDataStable_A	211061742	1538	0	111
gen_edn_if_asserts[3].EdnEndPointOut_A	211061742	210956477	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	211061742	90681	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	211061742	525952	0	302
gen_edn_if_asserts[4].EdnDataStable_A	211061742	3693	0	105
gen_edn_if_asserts[4].EdnEndPointOut_A	211061742	210956477	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	211061742	90681	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	211061742	525952	0	302
gen_edn_if_asserts[5].EdnDataStable_A	211061742	3334	0	98
gen_edn_if_asserts[5].EdnEndPointOut_A	211061742	210956477	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	211061742	90681	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	211061742	525952	0	302
gen_edn_if_asserts[6].EdnDataStable_A	211061742	1651	0	85
gen_edn_if_asserts[6].EdnEndPointOut_A	211061742	210956477	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	211061742	90681	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	210956477	0	0
T1	3909	3723	0	0
T2	2243	2165	0	0
T3	3723	3666	0	0
T8	2781	2690	0	0
T16	1551	1491	0	0
T21	2540	2472	0	0
T23	1558	1475	0	0
T27	2196	2131	0	0
T43	3770	3705	0	0
T47	1310	1253	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	210956477	0	0
T1	3909	3723	0	0
T2	2243	2165	0	0
T3	3723	3666	0	0
T8	2781	2690	0	0
T16	1551	1491	0	0
T21	2540	2472	0	0
T23	1558	1475	0	0
T27	2196	2131	0	0
T43	3770	3705	0	0
T47	1310	1253	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	38	0	0
T4	1493	1	0	0
T5	1618	0	0	0
T14	0	1	0	0
T15	0	1	0	0
T22	1199	0	0	0
T30	1941	0	0	0
T34	1437	0	0	0
T45	5817	0	0	0
T46	18940	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	1068	0	0	0
T56	5657	0	0	0
T57	1685	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	210956477	0	0
T1	3909	3723	0	0
T2	2243	2165	0	0
T3	3723	3666	0	0
T8	2781	2690	0	0
T16	1551	1491	0	0
T21	2540	2472	0	0
T23	1558	1475	0	0
T27	2196	2131	0	0
T43	3770	3705	0	0
T47	1310	1253	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	210956477	0	0
T1	3909	3723	0	0
T2	2243	2165	0	0
T3	3723	3666	0	0
T8	2781	2690	0	0
T16	1551	1491	0	0
T21	2540	2472	0	0
T23	1558	1475	0	0
T27	2196	2131	0	0
T43	3770	3705	0	0
T47	1310	1253	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	210956477	0	0
T1	3909	3723	0	0
T2	2243	2165	0	0
T3	3723	3666	0	0
T8	2781	2690	0	0
T16	1551	1491	0	0
T21	2540	2472	0	0
T23	1558	1475	0	0
T27	2196	2131	0	0
T43	3770	3705	0	0
T47	1310	1253	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	525952	0	302
T1	3909	900	0	0
T2	2243	306	0	0
T3	3723	18	0	0
T8	2781	225	0	0
T10	0	0	0	2
T16	1551	281	0	0
T17	0	0	0	2
T21	2540	238	0	0
T23	1558	1473	0	2
T24	0	0	0	2
T26	0	0	0	2
T27	2196	15	0	0
T43	3770	115	0	0
T47	1310	39	0	0
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	78197	0	420
T1	3909	3	0	1
T2	2243	4	0	0
T3	3723	23	0	1
T8	2781	8	0	1
T9	0	495	0	1
T16	1551	8	0	1
T21	2540	8	0	1
T23	1558	0	0	0
T27	2196	37	0	1
T28	0	0	0	1
T43	3770	9	0	1
T47	1310	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	210956477	0	0
T1	3909	3723	0	0
T2	2243	2165	0	0
T3	3723	3666	0	0
T8	2781	2690	0	0
T16	1551	1491	0	0
T21	2540	2472	0	0
T23	1558	1475	0	0
T27	2196	2131	0	0
T43	3770	3705	0	0
T47	1310	1253	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	90681	0	0
T4	1493	419	0	0
T5	1618	1002	0	0
T6	0	318	0	0
T7	0	1074	0	0
T14	0	614	0	0
T15	0	254	0	0
T22	1199	642	0	0
T30	1941	0	0	0
T34	1437	0	0	0
T45	5817	0	0	0
T46	18940	0	0	0
T55	1068	0	0	0
T56	5657	0	0	0
T57	1685	0	0	0
T63	0	592	0	0
T64	0	1101	0	0
T65	0	898	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	525952	0	302
T1	3909	900	0	0
T2	2243	306	0	0
T3	3723	18	0	0
T8	2781	225	0	0
T10	0	0	0	2
T16	1551	281	0	0
T17	0	0	0	2
T21	2540	238	0	0
T23	1558	1473	0	2
T24	0	0	0	2
T26	0	0	0	2
T27	2196	15	0	0
T43	3770	115	0	0
T47	1310	39	0	0
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	5606	0	148
T4	1493	1	0	0
T5	1618	0	0	0
T6	0	1	0	0
T9	4327	0	0	0
T10	2618	4	0	0
T22	1199	0	0	0
T23	1558	0	0	0
T27	2196	37	0	1
T28	2066	0	0	0
T29	4026	0	0	0
T30	1941	0	0	0
T31	0	28	0	1
T32	0	0	0	1
T33	0	3	0	1
T34	0	33	0	1
T39	0	3	0	1
T44	0	4	0	1
T57	0	3	0	1
T66	0	0	0	1
T67	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	210956477	0	0
T1	3909	3723	0	0
T2	2243	2165	0	0
T3	3723	3666	0	0
T8	2781	2690	0	0
T16	1551	1491	0	0
T21	2540	2472	0	0
T23	1558	1475	0	0
T27	2196	2131	0	0
T43	3770	3705	0	0
T47	1310	1253	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	90681	0	0
T4	1493	419	0	0
T5	1618	1002	0	0
T6	0	318	0	0
T7	0	1074	0	0
T14	0	614	0	0
T15	0	254	0	0
T22	1199	642	0	0
T30	1941	0	0	0
T34	1437	0	0	0
T45	5817	0	0	0
T46	18940	0	0	0
T55	1068	0	0	0
T56	5657	0	0	0
T57	1685	0	0	0
T63	0	592	0	0
T64	0	1101	0	0
T65	0	898	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	525952	0	302
T1	3909	900	0	0
T2	2243	306	0	0
T3	3723	18	0	0
T8	2781	225	0	0
T10	0	0	0	2
T16	1551	281	0	0
T17	0	0	0	2
T21	2540	238	0	0
T23	1558	1473	0	2
T24	0	0	0	2
T26	0	0	0	2
T27	2196	15	0	0
T43	3770	115	0	0
T47	1310	39	0	0
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	6130	0	127
T4	1493	0	0	0
T5	1618	0	0	0
T10	2618	0	0	0
T18	0	158	0	1
T22	1199	0	0	0
T28	2066	25	0	1
T29	4026	3	0	1
T30	1941	8	0	1
T31	0	41	0	1
T32	0	3	0	1
T33	0	3	0	1
T34	0	3	0	1
T35	0	14	0	1
T40	0	3	0	1
T45	5817	0	0	0
T55	1068	0	0	0
T56	5657	0	0	0

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	210956477	0	0
T1	3909	3723	0	0
T2	2243	2165	0	0
T3	3723	3666	0	0
T8	2781	2690	0	0
T16	1551	1491	0	0
T21	2540	2472	0	0
T23	1558	1475	0	0
T27	2196	2131	0	0
T43	3770	3705	0	0
T47	1310	1253	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	90681	0	0
T4	1493	419	0	0
T5	1618	1002	0	0
T6	0	318	0	0
T7	0	1074	0	0
T14	0	614	0	0
T15	0	254	0	0
T22	1199	642	0	0
T30	1941	0	0	0
T34	1437	0	0	0
T45	5817	0	0	0
T46	18940	0	0	0
T55	1068	0	0	0
T56	5657	0	0	0
T57	1685	0	0	0
T63	0	592	0	0
T64	0	1101	0	0
T65	0	898	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	525952	0	302
T1	3909	900	0	0
T2	2243	306	0	0
T3	3723	18	0	0
T8	2781	225	0	0
T10	0	0	0	2
T16	1551	281	0	0
T17	0	0	0	2
T21	2540	238	0	0
T23	1558	1473	0	2
T24	0	0	0	2
T26	0	0	0	2
T27	2196	15	0	0
T43	3770	115	0	0
T47	1310	39	0	0
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	1538	0	111
T2	2243	4	0	1
T3	3723	0	0	0
T8	2781	0	0	0
T9	4327	0	0	0
T16	1551	0	0	0
T21	2540	0	0	0
T23	1558	0	0	0
T27	2196	3	0	1
T28	0	3	0	1
T33	0	3	0	1
T36	0	4	0	0
T37	0	22	0	1
T39	0	3	0	1
T41	0	0	0	1
T43	3770	0	0	0
T47	1310	0	0	0
T68	0	4	0	1
T69	0	3	0	1
T70	0	3	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	210956477	0	0
T1	3909	3723	0	0
T2	2243	2165	0	0
T3	3723	3666	0	0
T8	2781	2690	0	0
T16	1551	1491	0	0
T21	2540	2472	0	0
T23	1558	1475	0	0
T27	2196	2131	0	0
T43	3770	3705	0	0
T47	1310	1253	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	90681	0	0
T4	1493	419	0	0
T5	1618	1002	0	0
T6	0	318	0	0
T7	0	1074	0	0
T14	0	614	0	0
T15	0	254	0	0
T22	1199	642	0	0
T30	1941	0	0	0
T34	1437	0	0	0
T45	5817	0	0	0
T46	18940	0	0	0
T55	1068	0	0	0
T56	5657	0	0	0
T57	1685	0	0	0
T63	0	592	0	0
T64	0	1101	0	0
T65	0	898	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	525952	0	302
T1	3909	900	0	0
T2	2243	306	0	0
T3	3723	18	0	0
T8	2781	225	0	0
T10	0	0	0	2
T16	1551	281	0	0
T17	0	0	0	2
T21	2540	238	0	0
T23	1558	1473	0	2
T24	0	0	0	2
T26	0	0	0	2
T27	2196	15	0	0
T43	3770	115	0	0
T47	1310	39	0	0
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	3693	0	105
T4	1493	0	0	0
T5	1618	0	0	0
T9	4327	0	0	0
T10	2618	0	0	0
T22	1199	0	0	0
T23	1558	0	0	0
T27	2196	49	0	1
T28	2066	0	0	0
T29	4026	0	0	0
T30	1941	0	0	0
T31	0	3	0	1
T32	0	33	0	1
T37	0	3	0	1
T38	0	53	0	1
T40	0	7	0	1
T42	0	3	0	1
T69	0	55	0	1
T70	0	25	0	1
T71	0	15	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	210956477	0	0
T1	3909	3723	0	0
T2	2243	2165	0	0
T3	3723	3666	0	0
T8	2781	2690	0	0
T16	1551	1491	0	0
T21	2540	2472	0	0
T23	1558	1475	0	0
T27	2196	2131	0	0
T43	3770	3705	0	0
T47	1310	1253	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	90681	0	0
T4	1493	419	0	0
T5	1618	1002	0	0
T6	0	318	0	0
T7	0	1074	0	0
T14	0	614	0	0
T15	0	254	0	0
T22	1199	642	0	0
T30	1941	0	0	0
T34	1437	0	0	0
T45	5817	0	0	0
T46	18940	0	0	0
T55	1068	0	0	0
T56	5657	0	0	0
T57	1685	0	0	0
T63	0	592	0	0
T64	0	1101	0	0
T65	0	898	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	525952	0	302
T1	3909	900	0	0
T2	2243	306	0	0
T3	3723	18	0	0
T8	2781	225	0	0
T10	0	0	0	2
T16	1551	281	0	0
T17	0	0	0	2
T21	2540	238	0	0
T23	1558	1473	0	2
T24	0	0	0	2
T26	0	0	0	2
T27	2196	15	0	0
T43	3770	115	0	0
T47	1310	39	0	0
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	3334	0	98
T4	1493	0	0	0
T5	1618	0	0	0
T9	4327	0	0	0
T10	2618	0	0	0
T17	0	4	0	0
T20	0	87	0	1
T22	1199	0	0	0
T23	1558	0	0	0
T27	2196	3	0	1
T28	2066	0	0	0
T29	4026	0	0	0
T30	1941	28	0	1
T32	0	11	0	1
T33	0	5	0	1
T38	0	3	0	1
T40	0	9	0	1
T42	0	7	0	1
T69	0	3	0	1
T71	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	210956477	0	0
T1	3909	3723	0	0
T2	2243	2165	0	0
T3	3723	3666	0	0
T8	2781	2690	0	0
T16	1551	1491	0	0
T21	2540	2472	0	0
T23	1558	1475	0	0
T27	2196	2131	0	0
T43	3770	3705	0	0
T47	1310	1253	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	90681	0	0
T4	1493	419	0	0
T5	1618	1002	0	0
T6	0	318	0	0
T7	0	1074	0	0
T14	0	614	0	0
T15	0	254	0	0
T22	1199	642	0	0
T30	1941	0	0	0
T34	1437	0	0	0
T45	5817	0	0	0
T46	18940	0	0	0
T55	1068	0	0	0
T56	5657	0	0	0
T57	1685	0	0	0
T63	0	592	0	0
T64	0	1101	0	0
T65	0	898	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	525952	0	302
T1	3909	900	0	0
T2	2243	306	0	0
T3	3723	18	0	0
T8	2781	225	0	0
T10	0	0	0	2
T16	1551	281	0	0
T17	0	0	0	2
T21	2540	238	0	0
T23	1558	1473	0	2
T24	0	0	0	2
T26	0	0	0	2
T27	2196	15	0	0
T43	3770	115	0	0
T47	1310	39	0	0
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	1651	0	85
T4	1493	0	0	0
T5	1618	0	0	0
T10	2618	1	0	0
T22	1199	0	0	0
T29	4026	0	0	0
T30	1941	0	0	0
T32	0	3	0	1
T33	0	11	0	1
T38	0	18	0	1
T41	0	3	0	1
T42	0	39	0	1
T45	5817	0	0	0
T46	18940	0	0	0
T55	1068	0	0	0
T56	5657	0	0	0
T72	0	15	0	1
T73	0	4	0	1
T74	0	3	0	1
T75	0	28	0	1
T76	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	210956477	0	0
T1	3909	3723	0	0
T2	2243	2165	0	0
T3	3723	3666	0	0
T8	2781	2690	0	0
T16	1551	1491	0	0
T21	2540	2472	0	0
T23	1558	1475	0	0
T27	2196	2131	0	0
T43	3770	3705	0	0
T47	1310	1253	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211061742	90681	0	0
T4	1493	419	0	0
T5	1618	1002	0	0
T6	0	318	0	0
T7	0	1074	0	0
T14	0	614	0	0
T15	0	254	0	0
T22	1199	642	0	0
T30	1941	0	0	0
T34	1437	0	0	0
T45	5817	0	0	0
T46	18940	0	0	0
T55	1068	0	0	0
T56	5657	0	0	0
T57	1685	0	0	0
T63	0	592	0	0
T64	0	1101	0	0
T65	0	898	0	0