Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.67		66.67	100.00			72.34	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	211566605	9139713	0	0
boot_gen_cmd_rd_A	211566605	70705	0	0
boot_ins_cmd_rd_A	211566605	80550	0	0
ctrl_rd_A	211566605	71817	0	0
err_code_test_rd_A	211566605	79789	0	0
intr_enable_rd_A	211566605	79138	0	0
max_num_reqs_between_reseeds_rd_A	211566605	70972	0	0
regwen_rd_A	211566605	81736	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211566605	9139713	0	0
T17	3451	0	0	0
T19	2711	0	0	0
T24	455823	260845	0	0
T25	0	51036	0	0
T26	0	136303	0	0
T31	2217	0	0	0
T35	4426	0	0	0
T39	3136	0	0	0
T59	0	331038	0	0
T60	0	232055	0	0
T91	2146	0	0	0
T92	1563	0	0	0
T105	1521	0	0	0
T229	0	75011	0	0
T230	0	219488	0	0
T231	0	313226	0	0
T232	0	105827	0	0
T233	0	184940	0	0
T234	1042	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211566605	70705	0	0
T38	2601	0	0	0
T60	686365	6496	0	0
T61	3268	0	0	0
T62	2216	0	0	0
T109	1593	0	0	0
T111	1564	0	0	0
T191	2542	0	0	0
T194	2187	0	0	0
T229	185834	0	0	0
T230	540396	0	0	0
T232	0	1595	0	0
T233	0	5166	0	0
T235	0	2170	0	0
T236	0	7448	0	0
T237	0	3656	0	0
T238	0	5431	0	0
T239	0	4230	0	0
T240	0	2614	0	0
T241	0	1049	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211566605	80550	0	0
T38	2601	0	0	0
T60	686365	7550	0	0
T61	3268	0	0	0
T62	2216	0	0	0
T109	1593	0	0	0
T111	1564	0	0	0
T191	2542	0	0	0
T194	2187	0	0	0
T229	185834	0	0	0
T230	540396	0	0	0
T232	0	1789	0	0
T233	0	5788	0	0
T235	0	2849	0	0
T236	0	8946	0	0
T237	0	4124	0	0
T238	0	5359	0	0
T239	0	4965	0	0
T240	0	3096	0	0
T241	0	1224	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211566605	71817	0	0
T38	2601	0	0	0
T60	686365	6890	0	0
T61	3268	0	0	0
T62	2216	0	0	0
T71	0	7	0	0
T109	1593	0	0	0
T111	1564	0	0	0
T191	2542	0	0	0
T194	2187	0	0	0
T229	185834	0	0	0
T230	540396	0	0	0
T232	0	1632	0	0
T233	0	5316	0	0
T235	0	2279	0	0
T236	0	7635	0	0
T237	0	3589	0	0
T242	0	2	0	0
T243	0	3	0	0
T244	0	1	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211566605	79789	0	0
T38	2601	0	0	0
T60	686365	7647	0	0
T61	3268	0	0	0
T62	2216	0	0	0
T109	1593	0	0	0
T111	1564	0	0	0
T191	2542	0	0	0
T194	2187	0	0	0
T229	185834	0	0	0
T230	540396	0	0	0
T232	0	1965	0	0
T233	0	6055	0	0
T235	0	2299	0	0
T236	0	8629	0	0
T237	0	4141	0	0
T238	0	5670	0	0
T239	0	4736	0	0
T240	0	2823	0	0
T241	0	1291	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211566605	79138	0	0
T1	3909	19	0	0
T2	2243	0	0	0
T3	3723	0	0	0
T8	2781	0	0	0
T16	1551	0	0	0
T21	2540	0	0	0
T23	1558	0	0	0
T27	2196	0	0	0
T43	3770	0	0	0
T46	0	99	0	0
T47	1310	0	0	0
T60	0	7160	0	0
T232	0	1763	0	0
T233	0	5834	0	0
T235	0	2663	0	0
T236	0	8159	0	0
T237	0	4085	0	0
T245	0	73	0	0
T246	0	23	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211566605	70972	0	0
T38	2601	0	0	0
T60	686365	6733	0	0
T61	3268	0	0	0
T62	2216	0	0	0
T109	1593	0	0	0
T111	1564	0	0	0
T191	2542	0	0	0
T194	2187	0	0	0
T229	185834	0	0	0
T230	540396	0	0	0
T232	0	1550	0	0
T233	0	5093	0	0
T235	0	2406	0	0
T236	0	7691	0	0
T237	0	3862	0	0
T238	0	5016	0	0
T239	0	4103	0	0
T240	0	2734	0	0
T241	0	1098	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211566605	81736	0	0
T38	2601	0	0	0
T60	686365	7489	0	0
T61	3268	0	0	0
T62	2216	0	0	0
T109	1593	0	0	0
T111	1564	0	0	0
T191	2542	0	0	0
T194	2187	0	0	0
T229	185834	0	0	0
T230	540396	0	0	0
T232	0	1922	0	0
T233	0	6152	0	0
T235	0	2714	0	0
T236	0	8755	0	0
T237	0	4307	0	0
T238	0	5768	0	0
T239	0	4917	0	0
T240	0	2947	0	0
T241	0	1203	0	0