Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.67 66.67 100.00 72.34

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 79.67 66.67 100.00 72.34



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.67 66.67 100.00 72.34


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.70 98.25 93.31 91.10 87.21 95.50 96.83


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
edn_csr_assert 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_edn_core 87.34 99.92 92.06 48.52 87.21 97.42 98.88
u_edn_cov_if 25.00 50.00 0.00
u_reg 96.77 95.02 97.16 99.53 92.16 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Cond Coverage for Module : edn
TotalCoveredPercent
Conditions6466.67
Logical6466.67
Non-Logical00
Event00

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT2,T18,T19

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT3,T4,T5

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 69 69 100.00
Total Bits 1172 1172 100.00
Total Bits 0->1 586 586 100.00
Total Bits 1->0 586 586 100.00

Ports 69 69 100.00
Port Bits 1172 1172 100.00
Port Bits 0->1 586 586 100.00
Port Bits 1->0 586 586 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T3,T8 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T18 Yes T1,T2,T18 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T20 Yes T1,T2,T8 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T8 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T21,T22,T23 Yes T21,T22,T23 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T8 Yes T1,T2,T8 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T1,T2,T8 Yes T1,T2,T8 INPUT
edn_i[1].edn_req Yes Yes T1,T8,T24 Yes T1,T8,T24 INPUT
edn_i[2].edn_req Yes Yes T1,T8,T24 Yes T1,T8,T24 INPUT
edn_i[3].edn_req Yes Yes T8,T24,T25 Yes T8,T24,T25 INPUT
edn_i[4].edn_req Yes Yes T8,T24,T25 Yes T8,T24,T25 INPUT
edn_i[5].edn_req Yes Yes T8,T4,T24 Yes T8,T4,T24 INPUT
edn_i[6].edn_req Yes Yes T3,T8,T25 Yes T3,T8,T25 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T1,T2,T8 Yes T1,T2,T8 OUTPUT
edn_o[0].edn_fips Yes Yes T9,T26,T27 Yes T2,T8,T9 OUTPUT
edn_o[0].edn_ack Yes Yes T1,T2,T8 Yes T1,T2,T8 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T8,T24,T14 Yes T1,T8,T24 OUTPUT
edn_o[1].edn_fips Yes Yes T28,T29,T30 Yes T28,T25,T29 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T8,T24 Yes T1,T8,T24 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T1,T24,T31 Yes T1,T8,T24 OUTPUT
edn_o[2].edn_fips Yes Yes T1,T24,T32 Yes T1,T8,T24 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T8,T24 Yes T1,T8,T24 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T25,T33,T34 Yes T8,T25,T35 OUTPUT
edn_o[3].edn_fips Yes Yes T25,T35,T33 Yes T8,T25,T35 OUTPUT
edn_o[3].edn_ack Yes Yes T8,T24,T25 Yes T8,T24,T25 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T8,T24,T25 Yes T8,T24,T25 OUTPUT
edn_o[4].edn_fips Yes Yes T24,T36,T33 Yes T8,T24,T36 OUTPUT
edn_o[4].edn_ack Yes Yes T8,T24,T25 Yes T8,T24,T25 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T8,T24,T33 Yes T8,T24,T33 OUTPUT
edn_o[5].edn_fips Yes Yes T24,T33,T37 Yes T8,T24,T33 OUTPUT
edn_o[5].edn_ack Yes Yes T8,T24,T33 Yes T8,T24,T33 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T8,T17,T38 Yes T8,T25,T17 OUTPUT
edn_o[6].edn_fips Yes Yes T8,T39,T32 Yes T8,T25,T17 OUTPUT
edn_o[6].edn_ack Yes Yes T8,T25,T17 Yes T8,T25,T17 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T8,T9 Yes T1,T2,T8 INPUT
csrng_cmd_i.genbits_fips Yes Yes T1,T8,T9 Yes T1,T2,T8 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T8 Yes T1,T2,T8 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] Yes Yes T2,T19,T40 Yes T2,T19,T40 INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T2,T18,T19 Yes T2,T18,T19 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T2,T18,T19 Yes T2,T18,T19 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T3,T4,T5 Yes T3,T4,T5 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T27,T41,T21 Yes T27,T41,T21 OUTPUT
intr_edn_fatal_err_o Yes Yes T27,T41,T21 Yes T27,T41,T21 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : edn
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 47 47 100.00 34 72.34
Cover properties 0 0 0
Cover sequences 0 0 0
Total 47 47 100.00 34 72.34




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AlertTxKnownO_A 238053005 237949948 0 0
CsrngAppIfOut_A 238053005 237949948 0 0
FpvSecCmCntAlertCheck_A 238053005 36 0 0
FpvSecCmGenCmdFifoRptrCheck_A 238053005 0 0 0
FpvSecCmGenCmdFifoWptrCheck_A 238053005 0 0 0
FpvSecCmMainFsmCheck_A 238053005 0 0 0
FpvSecCmRegWeOnehotCheck_A 238053005 0 0 0
FpvSecCmResCmdFifoRptrCheck_A 238053005 0 0 0
FpvSecCmResCmdFifoWptrCheck_A 238053005 0 0 0
IntrEdnCmdReqDoneKnownO_A 238053005 237949948 0 0
TlAReadyKnownO_A 238053005 237949948 0 0
TlDValidKnownO_A 238053005 237949948 0 0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A 238053005 0 0 0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A 238053005 0 0 0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A 238053005 0 0 0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A 238053005 0 0 0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A 238053005 0 0 0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A 238053005 0 0 0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A 238053005 0 0 0
gen_edn_if_asserts[0].EdnDataStableDisable_A 238053005 484409 0 300
gen_edn_if_asserts[0].EdnDataStable_A 238053005 21566 0 417
gen_edn_if_asserts[0].EdnEndPointOut_A 238053005 237949948 0 0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A 238053005 86499 0 0
gen_edn_if_asserts[1].EdnDataStableDisable_A 238053005 484409 0 300
gen_edn_if_asserts[1].EdnDataStable_A 238053005 6440 0 141
gen_edn_if_asserts[1].EdnEndPointOut_A 238053005 237949948 0 0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A 238053005 86499 0 0
gen_edn_if_asserts[2].EdnDataStableDisable_A 238053005 484409 0 300
gen_edn_if_asserts[2].EdnDataStable_A 238053005 4752 0 132
gen_edn_if_asserts[2].EdnEndPointOut_A 238053005 237949948 0 0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A 238053005 86499 0 0
gen_edn_if_asserts[3].EdnDataStableDisable_A 238053005 484409 0 300
gen_edn_if_asserts[3].EdnDataStable_A 238053005 4085 0 128
gen_edn_if_asserts[3].EdnEndPointOut_A 238053005 237949948 0 0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A 238053005 86499 0 0
gen_edn_if_asserts[4].EdnDataStableDisable_A 238053005 484409 0 300
gen_edn_if_asserts[4].EdnDataStable_A 238053005 3414 0 123
gen_edn_if_asserts[4].EdnEndPointOut_A 238053005 237949948 0 0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A 238053005 86499 0 0
gen_edn_if_asserts[5].EdnDataStableDisable_A 238053005 484409 0 300
gen_edn_if_asserts[5].EdnDataStable_A 238053005 1792 0 97
gen_edn_if_asserts[5].EdnEndPointOut_A 238053005 237949948 0 0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A 238053005 86499 0 0
gen_edn_if_asserts[6].EdnDataStableDisable_A 238053005 484409 0 300
gen_edn_if_asserts[6].EdnDataStable_A 238053005 54936 0 96
gen_edn_if_asserts[6].EdnEndPointOut_A 238053005 237949948 0 0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A 238053005 86499 0 0


AlertTxKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 237949948 0 0
T1 2763 2670 0 0
T2 1891 1803 0 0
T3 1165 1027 0 0
T4 1401 1245 0 0
T8 5050 4952 0 0
T9 2991 2916 0 0
T18 2288 2231 0 0
T19 2064 2004 0 0
T20 1889 1822 0 0
T24 3641 3573 0 0

CsrngAppIfOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 237949948 0 0
T1 2763 2670 0 0
T2 1891 1803 0 0
T3 1165 1027 0 0
T4 1401 1245 0 0
T8 5050 4952 0 0
T9 2991 2916 0 0
T18 2288 2231 0 0
T19 2064 2004 0 0
T20 1889 1822 0 0
T24 3641 3573 0 0

FpvSecCmCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 36 0 0
T4 1401 1 0 0
T5 558 0 0 0
T6 2174 0 0 0
T7 0 1 0 0
T13 0 1 0 0
T14 2380 0 0 0
T19 2064 0 0 0
T24 3641 0 0 0
T26 3038 0 0 0
T31 1123 0 0 0
T42 0 1 0 0
T43 0 1 0 0
T44 0 1 0 0
T45 0 1 0 0
T46 0 1 0 0
T47 0 1 0 0
T48 0 1 0 0
T49 954 0 0 0
T50 1520 0 0 0

FpvSecCmGenCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 0 0 0

FpvSecCmGenCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 0 0 0

FpvSecCmMainFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 0 0 0

FpvSecCmResCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 0 0 0

FpvSecCmResCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 0 0 0

IntrEdnCmdReqDoneKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 237949948 0 0
T1 2763 2670 0 0
T2 1891 1803 0 0
T3 1165 1027 0 0
T4 1401 1245 0 0
T8 5050 4952 0 0
T9 2991 2916 0 0
T18 2288 2231 0 0
T19 2064 2004 0 0
T20 1889 1822 0 0
T24 3641 3573 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 237949948 0 0
T1 2763 2670 0 0
T2 1891 1803 0 0
T3 1165 1027 0 0
T4 1401 1245 0 0
T8 5050 4952 0 0
T9 2991 2916 0 0
T18 2288 2231 0 0
T19 2064 2004 0 0
T20 1889 1822 0 0
T24 3641 3573 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 237949948 0 0
T1 2763 2670 0 0
T2 1891 1803 0 0
T3 1165 1027 0 0
T4 1401 1245 0 0
T8 5050 4952 0 0
T9 2991 2916 0 0
T18 2288 2231 0 0
T19 2064 2004 0 0
T20 1889 1822 0 0
T24 3641 3573 0 0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 0 0 0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 0 0 0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 0 0 0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 0 0 0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 0 0 0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 0 0 0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 0 0 0

gen_edn_if_asserts[0].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 484409 0 300
T1 2763 19 0 0
T2 1891 178 0 0
T3 1165 612 0 0
T4 1401 880 0 0
T8 5050 292 0 0
T9 2991 69 0 0
T14 0 0 0 2
T17 0 0 0 2
T18 2288 282 0 0
T19 2064 178 0 0
T20 1889 14 0 0
T21 0 0 0 2
T22 0 0 0 2
T24 3641 18 0 0
T50 0 0 0 2
T51 0 0 0 2
T52 0 0 0 2
T53 0 0 0 2
T54 0 0 0 2
T55 0 0 0 2

gen_edn_if_asserts[0].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 21566 0 417
T1 2763 11 0 1
T2 1891 4 0 1
T3 1165 0 0 0
T4 1401 0 0 0
T8 5050 3 0 1
T9 2991 431 0 1
T18 2288 4 0 1
T19 2064 8 0 1
T20 1889 3 0 1
T24 3641 3 0 1
T26 0 44 0 1
T49 0 3 0 1

gen_edn_if_asserts[0].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 237949948 0 0
T1 2763 2670 0 0
T2 1891 1803 0 0
T3 1165 1027 0 0
T4 1401 1245 0 0
T8 5050 4952 0 0
T9 2991 2916 0 0
T18 2288 2231 0 0
T19 2064 2004 0 0
T20 1889 1822 0 0
T24 3641 3573 0 0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 86499 0 0
T3 1165 640 0 0
T4 1401 444 0 0
T5 0 262 0 0
T6 0 387 0 0
T7 0 661 0 0
T8 5050 0 0 0
T9 2991 0 0 0
T13 0 1157 0 0
T14 2380 0 0 0
T18 2288 0 0 0
T19 2064 0 0 0
T20 1889 0 0 0
T24 3641 0 0 0
T26 3038 0 0 0
T36 0 41 0 0
T56 0 639 0 0
T57 0 590 0 0
T58 0 249 0 0

gen_edn_if_asserts[1].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 484409 0 300
T1 2763 19 0 0
T2 1891 178 0 0
T3 1165 612 0 0
T4 1401 880 0 0
T8 5050 292 0 0
T9 2991 69 0 0
T14 0 0 0 2
T17 0 0 0 2
T18 2288 282 0 0
T19 2064 178 0 0
T20 1889 14 0 0
T21 0 0 0 2
T22 0 0 0 2
T24 3641 18 0 0
T50 0 0 0 2
T51 0 0 0 2
T52 0 0 0 2
T53 0 0 0 2
T54 0 0 0 2
T55 0 0 0 2

gen_edn_if_asserts[1].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 6440 0 141
T1 2763 3 0 1
T2 1891 0 0 0
T3 1165 0 0 0
T4 1401 0 0 0
T8 5050 3 0 1
T9 2991 0 0 0
T14 0 4 0 0
T16 0 3 0 1
T18 2288 0 0 0
T19 2064 0 0 0
T20 1889 0 0 0
T24 3641 3 0 1
T25 0 3 0 1
T28 0 4 0 0
T29 0 4 0 0
T30 0 0 0 1
T59 0 4 0 1
T60 0 4 0 1
T61 0 0 0 1
T62 0 0 0 1

gen_edn_if_asserts[1].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 237949948 0 0
T1 2763 2670 0 0
T2 1891 1803 0 0
T3 1165 1027 0 0
T4 1401 1245 0 0
T8 5050 4952 0 0
T9 2991 2916 0 0
T18 2288 2231 0 0
T19 2064 2004 0 0
T20 1889 1822 0 0
T24 3641 3573 0 0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 86499 0 0
T3 1165 640 0 0
T4 1401 444 0 0
T5 0 262 0 0
T6 0 387 0 0
T7 0 661 0 0
T8 5050 0 0 0
T9 2991 0 0 0
T13 0 1157 0 0
T14 2380 0 0 0
T18 2288 0 0 0
T19 2064 0 0 0
T20 1889 0 0 0
T24 3641 0 0 0
T26 3038 0 0 0
T36 0 41 0 0
T56 0 639 0 0
T57 0 590 0 0
T58 0 249 0 0

gen_edn_if_asserts[2].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 484409 0 300
T1 2763 19 0 0
T2 1891 178 0 0
T3 1165 612 0 0
T4 1401 880 0 0
T8 5050 292 0 0
T9 2991 69 0 0
T14 0 0 0 2
T17 0 0 0 2
T18 2288 282 0 0
T19 2064 178 0 0
T20 1889 14 0 0
T21 0 0 0 2
T22 0 0 0 2
T24 3641 18 0 0
T50 0 0 0 2
T51 0 0 0 2
T52 0 0 0 2
T53 0 0 0 2
T54 0 0 0 2
T55 0 0 0 2

gen_edn_if_asserts[2].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 4752 0 132
T1 2763 46 0 1
T2 1891 0 0 0
T3 1165 0 0 0
T4 1401 0 0 0
T8 5050 3 0 1
T9 2991 0 0 0
T18 2288 0 0 0
T19 2064 0 0 0
T20 1889 0 0 0
T24 3641 61 0 1
T25 0 3 0 1
T31 0 3 0 1
T32 0 0 0 1
T40 0 4 0 1
T51 0 4 0 0
T61 0 3 0 1
T63 0 4 0 1
T64 0 3 0 1

gen_edn_if_asserts[2].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 237949948 0 0
T1 2763 2670 0 0
T2 1891 1803 0 0
T3 1165 1027 0 0
T4 1401 1245 0 0
T8 5050 4952 0 0
T9 2991 2916 0 0
T18 2288 2231 0 0
T19 2064 2004 0 0
T20 1889 1822 0 0
T24 3641 3573 0 0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 86499 0 0
T3 1165 640 0 0
T4 1401 444 0 0
T5 0 262 0 0
T6 0 387 0 0
T7 0 661 0 0
T8 5050 0 0 0
T9 2991 0 0 0
T13 0 1157 0 0
T14 2380 0 0 0
T18 2288 0 0 0
T19 2064 0 0 0
T20 1889 0 0 0
T24 3641 0 0 0
T26 3038 0 0 0
T36 0 41 0 0
T56 0 639 0 0
T57 0 590 0 0
T58 0 249 0 0

gen_edn_if_asserts[3].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 484409 0 300
T1 2763 19 0 0
T2 1891 178 0 0
T3 1165 612 0 0
T4 1401 880 0 0
T8 5050 292 0 0
T9 2991 69 0 0
T14 0 0 0 2
T17 0 0 0 2
T18 2288 282 0 0
T19 2064 178 0 0
T20 1889 14 0 0
T21 0 0 0 2
T22 0 0 0 2
T24 3641 18 0 0
T50 0 0 0 2
T51 0 0 0 2
T52 0 0 0 2
T53 0 0 0 2
T54 0 0 0 2
T55 0 0 0 2

gen_edn_if_asserts[3].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 4085 0 128
T4 1401 0 0 0
T8 5050 3 0 1
T9 2991 0 0 0
T14 2380 0 0 0
T18 2288 0 0 0
T19 2064 0 0 0
T20 1889 0 0 0
T24 3641 3 0 1
T25 0 40 0 1
T26 3038 0 0 0
T31 1123 0 0 0
T32 0 3 0 1
T33 0 29 0 1
T34 0 4 0 1
T35 0 3 0 1
T61 0 3 0 1
T62 0 20 0 1
T65 0 3 0 1

gen_edn_if_asserts[3].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 237949948 0 0
T1 2763 2670 0 0
T2 1891 1803 0 0
T3 1165 1027 0 0
T4 1401 1245 0 0
T8 5050 4952 0 0
T9 2991 2916 0 0
T18 2288 2231 0 0
T19 2064 2004 0 0
T20 1889 1822 0 0
T24 3641 3573 0 0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 86499 0 0
T3 1165 640 0 0
T4 1401 444 0 0
T5 0 262 0 0
T6 0 387 0 0
T7 0 661 0 0
T8 5050 0 0 0
T9 2991 0 0 0
T13 0 1157 0 0
T14 2380 0 0 0
T18 2288 0 0 0
T19 2064 0 0 0
T20 1889 0 0 0
T24 3641 0 0 0
T26 3038 0 0 0
T36 0 41 0 0
T56 0 639 0 0
T57 0 590 0 0
T58 0 249 0 0

gen_edn_if_asserts[4].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 484409 0 300
T1 2763 19 0 0
T2 1891 178 0 0
T3 1165 612 0 0
T4 1401 880 0 0
T8 5050 292 0 0
T9 2991 69 0 0
T14 0 0 0 2
T17 0 0 0 2
T18 2288 282 0 0
T19 2064 178 0 0
T20 1889 14 0 0
T21 0 0 0 2
T22 0 0 0 2
T24 3641 18 0 0
T50 0 0 0 2
T51 0 0 0 2
T52 0 0 0 2
T53 0 0 0 2
T54 0 0 0 2
T55 0 0 0 2

gen_edn_if_asserts[4].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 3414 0 123
T4 1401 0 0 0
T8 5050 11 0 1
T9 2991 0 0 0
T14 2380 0 0 0
T18 2288 0 0 0
T19 2064 0 0 0
T20 1889 0 0 0
T24 3641 44 0 1
T25 0 3 0 1
T26 3038 0 0 0
T31 1123 0 0 0
T32 0 33 0 1
T33 0 46 0 1
T36 0 1 0 0
T61 0 5 0 1
T62 0 55 0 1
T65 0 24 0 1
T66 0 3 0 1
T67 0 0 0 1

gen_edn_if_asserts[4].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 237949948 0 0
T1 2763 2670 0 0
T2 1891 1803 0 0
T3 1165 1027 0 0
T4 1401 1245 0 0
T8 5050 4952 0 0
T9 2991 2916 0 0
T18 2288 2231 0 0
T19 2064 2004 0 0
T20 1889 1822 0 0
T24 3641 3573 0 0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 86499 0 0
T3 1165 640 0 0
T4 1401 444 0 0
T5 0 262 0 0
T6 0 387 0 0
T7 0 661 0 0
T8 5050 0 0 0
T9 2991 0 0 0
T13 0 1157 0 0
T14 2380 0 0 0
T18 2288 0 0 0
T19 2064 0 0 0
T20 1889 0 0 0
T24 3641 0 0 0
T26 3038 0 0 0
T36 0 41 0 0
T56 0 639 0 0
T57 0 590 0 0
T58 0 249 0 0

gen_edn_if_asserts[5].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 484409 0 300
T1 2763 19 0 0
T2 1891 178 0 0
T3 1165 612 0 0
T4 1401 880 0 0
T8 5050 292 0 0
T9 2991 69 0 0
T14 0 0 0 2
T17 0 0 0 2
T18 2288 282 0 0
T19 2064 178 0 0
T20 1889 14 0 0
T21 0 0 0 2
T22 0 0 0 2
T24 3641 18 0 0
T50 0 0 0 2
T51 0 0 0 2
T52 0 0 0 2
T53 0 0 0 2
T54 0 0 0 2
T55 0 0 0 2

gen_edn_if_asserts[5].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 1792 0 97
T4 1401 0 0 0
T8 5050 15 0 1
T9 2991 0 0 0
T14 2380 0 0 0
T18 2288 0 0 0
T19 2064 0 0 0
T20 1889 0 0 0
T24 3641 32 0 1
T26 3038 0 0 0
T31 1123 0 0 0
T33 0 13 0 1
T37 0 33 0 1
T62 0 8 0 1
T65 0 3 0 1
T68 0 4 0 1
T69 0 3 0 1
T70 0 39 0 1
T71 0 3 0 1

gen_edn_if_asserts[5].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 237949948 0 0
T1 2763 2670 0 0
T2 1891 1803 0 0
T3 1165 1027 0 0
T4 1401 1245 0 0
T8 5050 4952 0 0
T9 2991 2916 0 0
T18 2288 2231 0 0
T19 2064 2004 0 0
T20 1889 1822 0 0
T24 3641 3573 0 0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 86499 0 0
T3 1165 640 0 0
T4 1401 444 0 0
T5 0 262 0 0
T6 0 387 0 0
T7 0 661 0 0
T8 5050 0 0 0
T9 2991 0 0 0
T13 0 1157 0 0
T14 2380 0 0 0
T18 2288 0 0 0
T19 2064 0 0 0
T20 1889 0 0 0
T24 3641 0 0 0
T26 3038 0 0 0
T36 0 41 0 0
T56 0 639 0 0
T57 0 590 0 0
T58 0 249 0 0

gen_edn_if_asserts[6].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 484409 0 300
T1 2763 19 0 0
T2 1891 178 0 0
T3 1165 612 0 0
T4 1401 880 0 0
T8 5050 292 0 0
T9 2991 69 0 0
T14 0 0 0 2
T17 0 0 0 2
T18 2288 282 0 0
T19 2064 178 0 0
T20 1889 14 0 0
T21 0 0 0 2
T22 0 0 0 2
T24 3641 18 0 0
T50 0 0 0 2
T51 0 0 0 2
T52 0 0 0 2
T53 0 0 0 2
T54 0 0 0 2
T55 0 0 0 2

gen_edn_if_asserts[6].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 54936 0 96
T4 1401 0 0 0
T8 5050 639 0 1
T9 2991 0 0 0
T14 2380 0 0 0
T17 0 4 0 0
T18 2288 0 0 0
T19 2064 0 0 0
T20 1889 0 0 0
T24 3641 0 0 0
T25 0 3 0 1
T26 3038 0 0 0
T31 1123 0 0 0
T32 0 44 0 1
T38 0 3 0 1
T39 0 6 0 1
T62 0 36 0 1
T65 0 3 0 1
T69 0 0 0 1
T72 0 4 0 1
T73 0 4 0 1

gen_edn_if_asserts[6].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 237949948 0 0
T1 2763 2670 0 0
T2 1891 1803 0 0
T3 1165 1027 0 0
T4 1401 1245 0 0
T8 5050 4952 0 0
T9 2991 2916 0 0
T18 2288 2231 0 0
T19 2064 2004 0 0
T20 1889 1822 0 0
T24 3641 3573 0 0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238053005 86499 0 0
T3 1165 640 0 0
T4 1401 444 0 0
T5 0 262 0 0
T6 0 387 0 0
T7 0 661 0 0
T8 5050 0 0 0
T9 2991 0 0 0
T13 0 1157 0 0
T14 2380 0 0 0
T18 2288 0 0 0
T19 2064 0 0 0
T20 1889 0 0 0
T24 3641 0 0 0
T26 3038 0 0 0
T36 0 41 0 0
T56 0 639 0 0
T57 0 590 0 0
T58 0 249 0 0