Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.67		66.67	100.00			72.34	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	238534003	10160548	0	0
boot_gen_cmd_rd_A	238534003	85084	0	0
boot_ins_cmd_rd_A	238534003	96817	0	0
ctrl_rd_A	238534003	85855	0	0
err_code_test_rd_A	238534003	97602	0	0
intr_enable_rd_A	238534003	93861	0	0
max_num_reqs_between_reseeds_rd_A	238534003	86157	0	0
regwen_rd_A	238534003	97846	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238534003	10160548	0	0
T7	1633	0	0	0
T13	1937	0	0	0
T21	298495	176007	0	0
T22	0	74370	0	0
T23	0	215831	0	0
T29	843	0	0	0
T35	1157	0	0	0
T40	2571	0	0	0
T51	2732	0	0	0
T54	0	264809	0	0
T56	1178	0	0	0
T59	1885	0	0	0
T63	2418	0	0	0
T223	0	3975	0	0
T224	0	74359	0	0
T225	0	121531	0	0
T226	0	594531	0	0
T227	0	135942	0	0
T228	0	135661	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238534003	85084	0	0
T70	2812	0	0	0
T126	1559	0	0	0
T137	2644	0	0	0
T138	2335	0	0	0
T173	2275	0	0	0
T186	2287	0	0	0
T208	1905	0	0	0
T223	104489	64	0	0
T224	0	1063	0	0
T225	0	3414	0	0
T227	0	4055	0	0
T228	0	3790	0	0
T229	0	4229	0	0
T230	0	5750	0	0
T231	0	1475	0	0
T232	0	5558	0	0
T233	0	3917	0	0
T234	1708	0	0	0
T235	4560	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238534003	96817	0	0
T70	2812	0	0	0
T126	1559	0	0	0
T137	2644	0	0	0
T138	2335	0	0	0
T173	2275	0	0	0
T186	2287	0	0	0
T208	1905	0	0	0
T223	104489	63	0	0
T224	0	1403	0	0
T225	0	4222	0	0
T227	0	4502	0	0
T228	0	4352	0	0
T229	0	4762	0	0
T230	0	6197	0	0
T231	0	1487	0	0
T232	0	6819	0	0
T233	0	4136	0	0
T234	1708	0	0	0
T235	4560	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238534003	85855	0	0
T22	193404	0	0	0
T42	903	0	0	0
T61	9541	0	0	0
T68	1773	0	0	0
T74	944	0	0	0
T77	1251	9	0	0
T96	1665	0	0	0
T133	2337	0	0	0
T136	1954	0	0	0
T223	0	58	0	0
T224	0	1329	0	0
T225	0	3480	0	0
T227	0	3705	0	0
T228	0	4167	0	0
T229	0	4063	0	0
T236	0	3	0	0
T237	0	4	0	0
T238	0	4	0	0
T239	1142	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238534003	97602	0	0
T70	2812	0	0	0
T126	1559	0	0	0
T137	2644	0	0	0
T138	2335	0	0	0
T173	2275	0	0	0
T186	2287	0	0	0
T208	1905	0	0	0
T223	104489	82	0	0
T224	0	1366	0	0
T225	0	4082	0	0
T227	0	4528	0	0
T228	0	4439	0	0
T229	0	4814	0	0
T230	0	6589	0	0
T231	0	1490	0	0
T232	0	6494	0	0
T233	0	4134	0	0
T234	1708	0	0	0
T235	4560	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238534003	93861	0	0
T70	2812	0	0	0
T126	1559	0	0	0
T137	2644	0	0	0
T138	2335	0	0	0
T173	2275	0	0	0
T186	2287	0	0	0
T208	1905	0	0	0
T223	104489	149	0	0
T224	0	1263	0	0
T225	0	3812	0	0
T227	0	4440	0	0
T228	0	4238	0	0
T229	0	4508	0	0
T230	0	5981	0	0
T234	1708	0	0	0
T235	4560	0	0	0
T237	0	66	0	0
T238	0	48	0	0
T240	0	48	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238534003	86157	0	0
T70	2812	0	0	0
T126	1559	0	0	0
T137	2644	0	0	0
T138	2335	0	0	0
T173	2275	0	0	0
T186	2287	0	0	0
T208	1905	0	0	0
T223	104489	58	0	0
T224	0	1250	0	0
T225	0	3520	0	0
T227	0	3916	0	0
T228	0	3928	0	0
T229	0	4186	0	0
T230	0	5697	0	0
T231	0	1296	0	0
T232	0	5581	0	0
T233	0	3733	0	0
T234	1708	0	0	0
T235	4560	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238534003	97846	0	0
T70	2812	0	0	0
T126	1559	0	0	0
T137	2644	0	0	0
T138	2335	0	0	0
T173	2275	0	0	0
T186	2287	0	0	0
T208	1905	0	0	0
T223	104489	30	0	0
T224	0	1395	0	0
T225	0	4401	0	0
T227	0	4361	0	0
T228	0	4438	0	0
T229	0	4496	0	0
T230	0	6391	0	0
T231	0	1504	0	0
T232	0	6703	0	0
T233	0	4311	0	0
T234	1708	0	0	0
T235	4560	0	0	0