Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	79.67		66.67	100.00			72.34

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.67		66.67	100.00			72.34

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.78	98.25	93.25	91.05	87.79	95.50	96.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	87.37	99.92	91.98	48.22	87.79	97.42	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.77	95.02	97.16	99.53		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T18,T11

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T5,T6

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T7	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T7,T19	Yes	T1,T7,T19	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T3,T7	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T7	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T3,T7,T19	Yes	T3,T7,T19	INPUT
edn_i[1].edn_req	Yes	Yes	T23,T13,T14	Yes	T23,T13,T14	INPUT
edn_i[2].edn_req	Yes	Yes	T12,T13,T18	Yes	T12,T13,T18	INPUT
edn_i[3].edn_req	Yes	Yes	T1,T14,T11	Yes	T1,T14,T11	INPUT
edn_i[4].edn_req	Yes	Yes	T13,T14,T24	Yes	T13,T14,T24	INPUT
edn_i[5].edn_req	Yes	Yes	T13,T14,T25	Yes	T13,T14,T25	INPUT
edn_i[6].edn_req	Yes	Yes	T14,T26,T27	Yes	T14,T26,T27	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T3,T19,T12	Yes	T3,T7,T19	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T12,T14	Yes	T3,T19,T12	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T3,T7,T19	Yes	T3,T7,T19	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T13,T14,T28	Yes	T13,T14,T28	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T14,T28,T29	Yes	T23,T14,T28	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T23,T13,T14	Yes	T23,T13,T14	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T12,T13,T18	Yes	T12,T13,T18	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T12,T13,T28	Yes	T12,T13,T28	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T12,T13,T18	Yes	T12,T13,T18	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T1,T14,T11	Yes	T1,T14,T11	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T27,T29,T30	Yes	T11,T24,T27	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T1,T14,T11	Yes	T1,T14,T11	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T13,T14,T24	Yes	T13,T14,T24	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T13,T25,T31	Yes	T13,T14,T24	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T13,T14,T24	Yes	T13,T14,T24	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T13,T14,T25	Yes	T13,T14,T25	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T13,T14,T25	Yes	T13,T14,T25	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T13,T14,T25	Yes	T13,T14,T25	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T14,T26,T27	Yes	T14,T26,T27	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T32,T33,T34	Yes	T14,T29,T32	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T14,T26,T27	Yes	T14,T26,T27	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T3,T12	Yes	T1,T3,T7	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T12,T13	Yes	T1,T12,T13	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T12,T13	Yes	T1,T12,T13	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T3,T18,T35	Yes	T3,T18,T35	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T3,T18	Yes	T2,T3,T18	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T3,T18	Yes	T2,T3,T18	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T20,T21,T36	Yes	T20,T21,T36	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T20,T21,T37	Yes	T20,T21,T37	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	34	72.34
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	34	72.34

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	209386385	209280204	0	0
CsrngAppIfOut_A	209386385	209280204	0	0
FpvSecCmCntAlertCheck_A	209386385	37	0	0
FpvSecCmGenCmdFifoRptrCheck_A	209386385	0	0	0
FpvSecCmGenCmdFifoWptrCheck_A	209386385	0	0	0
FpvSecCmMainFsmCheck_A	209386385	0	0	0
FpvSecCmRegWeOnehotCheck_A	209386385	0	0	0
FpvSecCmResCmdFifoRptrCheck_A	209386385	0	0	0
FpvSecCmResCmdFifoWptrCheck_A	209386385	0	0	0
IntrEdnCmdReqDoneKnownO_A	209386385	209280204	0	0
TlAReadyKnownO_A	209386385	209280204	0	0
TlDValidKnownO_A	209386385	209280204	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	209386385	0	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	209386385	0	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	209386385	0	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	209386385	0	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	209386385	0	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	209386385	0	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	209386385	0	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	209386385	467844	0	294
gen_edn_if_asserts[0].EdnDataStable_A	209386385	26951	0	435
gen_edn_if_asserts[0].EdnEndPointOut_A	209386385	209280204	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	209386385	85942	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	209386385	467844	0	294
gen_edn_if_asserts[1].EdnDataStable_A	209386385	5273	0	146
gen_edn_if_asserts[1].EdnEndPointOut_A	209386385	209280204	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	209386385	85942	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	209386385	467844	0	294
gen_edn_if_asserts[2].EdnDataStable_A	209386385	4638	0	138
gen_edn_if_asserts[2].EdnEndPointOut_A	209386385	209280204	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	209386385	85942	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	209386385	467844	0	294
gen_edn_if_asserts[3].EdnDataStable_A	209386385	5294	0	126
gen_edn_if_asserts[3].EdnEndPointOut_A	209386385	209280204	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	209386385	85942	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	209386385	467844	0	294
gen_edn_if_asserts[4].EdnDataStable_A	209386385	3427	0	110
gen_edn_if_asserts[4].EdnEndPointOut_A	209386385	209280204	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	209386385	85942	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	209386385	467844	0	294
gen_edn_if_asserts[5].EdnDataStable_A	209386385	3333	0	97
gen_edn_if_asserts[5].EdnEndPointOut_A	209386385	209280204	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	209386385	85942	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	209386385	467844	0	294
gen_edn_if_asserts[6].EdnDataStable_A	209386385	3465	0	89
gen_edn_if_asserts[6].EdnEndPointOut_A	209386385	209280204	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	209386385	85942	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	37	0	0
T8	575	1	0	0
T9	0	1	0	0
T15	0	1	0	0
T20	107028	0	0	0
T21	306230	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	2829	0	0	0
T46	3244	0	0	0
T47	2242	0	0	0
T48	2591	0	0	0
T49	2770	0	0	0
T50	1038	0	0	0
T51	776	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	467844	0	294
T1	2668	1438	0	2
T2	1493	1430	0	2
T3	1841	294	0	0
T7	1778	27	0	0
T10	2011	337	0	0
T12	2121	298	0	0
T13	4211	191	0	0
T14	4925	328	0	0
T16	0	0	0	2
T19	1842	20	0	0
T20	0	0	0	2
T21	0	0	0	2
T23	1147	58	0	0
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	26951	0	435
T3	1841	8	0	1
T7	1778	3	0	1
T10	2011	33	0	1
T11	1775	0	0	0
T12	2121	17	0	1
T13	4211	3	0	1
T14	4925	60	0	1
T16	0	4	0	0
T17	0	0	0	1
T18	1522	0	0	0
T19	1842	3	0	1
T23	1147	0	0	0
T35	0	8	0	1
T57	0	4	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	85942	0	0
T4	663	352	0	0
T5	1093	287	0	0
T6	653	322	0	0
T8	0	194	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T37	0	7	0	0
T51	0	422	0	0
T52	920	0	0	0
T58	0	666	0	0
T59	0	1002	0	0
T60	0	292	0	0
T61	0	7	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	467844	0	294
T1	2668	1438	0	2
T2	1493	1430	0	2
T3	1841	294	0	0
T7	1778	27	0	0
T10	2011	337	0	0
T12	2121	298	0	0
T13	4211	191	0	0
T14	4925	328	0	0
T16	0	0	0	2
T19	1842	20	0	0
T20	0	0	0	2
T21	0	0	0	2
T23	1147	58	0	0
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	5273	0	146
T10	2011	0	0	0
T11	1775	0	0	0
T13	4211	3	0	1
T14	4925	61	0	1
T16	1880	0	0	0
T18	1522	0	0	0
T23	1147	3	0	1
T25	0	3	0	1
T28	2534	19	0	1
T29	0	33	0	1
T35	1993	0	0	0
T57	2727	0	0	0
T65	0	4	0	1
T66	0	8	0	1
T67	0	3	0	1
T68	0	4	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	85942	0	0
T4	663	352	0	0
T5	1093	287	0	0
T6	653	322	0	0
T8	0	194	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T37	0	7	0	0
T51	0	422	0	0
T52	920	0	0	0
T58	0	666	0	0
T59	0	1002	0	0
T60	0	292	0	0
T61	0	7	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	467844	0	294
T1	2668	1438	0	2
T2	1493	1430	0	2
T3	1841	294	0	0
T7	1778	27	0	0
T10	2011	337	0	0
T12	2121	298	0	0
T13	4211	191	0	0
T14	4925	328	0	0
T16	0	0	0	2
T19	1842	20	0	0
T20	0	0	0	2
T21	0	0	0	2
T23	1147	58	0	0
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	4638	0	138
T10	2011	0	0	0
T11	1775	0	0	0
T12	2121	15	0	1
T13	4211	101	0	1
T14	4925	0	0	0
T16	1880	0	0	0
T18	1522	4	0	1
T23	1147	0	0	0
T25	0	3	0	1
T28	2534	12	0	1
T31	0	3	0	1
T57	2727	0	0	0
T66	0	80	0	1
T67	0	3	0	1
T68	0	4	0	0
T69	0	4	0	1
T70	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	85942	0	0
T4	663	352	0	0
T5	1093	287	0	0
T6	653	322	0	0
T8	0	194	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T37	0	7	0	0
T51	0	422	0	0
T52	920	0	0	0
T58	0	666	0	0
T59	0	1002	0	0
T60	0	292	0	0
T61	0	7	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	467844	0	294
T1	2668	1438	0	2
T2	1493	1430	0	2
T3	1841	294	0	0
T7	1778	27	0	0
T10	2011	337	0	0
T12	2121	298	0	0
T13	4211	191	0	0
T14	4925	328	0	0
T16	0	0	0	2
T19	1842	20	0	0
T20	0	0	0	2
T21	0	0	0	2
T23	1147	58	0	0
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	5294	0	126
T1	2668	4	0	0
T2	1493	0	0	0
T3	1841	0	0	0
T7	1778	0	0	0
T10	2011	0	0	0
T11	0	4	0	1
T12	2121	0	0	0
T13	4211	0	0	0
T14	4925	4	0	1
T19	1842	0	0	0
T23	1147	0	0	0
T24	0	3	0	1
T25	0	3	0	1
T27	0	45	0	1
T29	0	423	0	1
T30	0	0	0	1
T48	0	3	0	1
T66	0	3	0	1
T67	0	3	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	85942	0	0
T4	663	352	0	0
T5	1093	287	0	0
T6	653	322	0	0
T8	0	194	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T37	0	7	0	0
T51	0	422	0	0
T52	920	0	0	0
T58	0	666	0	0
T59	0	1002	0	0
T60	0	292	0	0
T61	0	7	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	467844	0	294
T1	2668	1438	0	2
T2	1493	1430	0	2
T3	1841	294	0	0
T7	1778	27	0	0
T10	2011	337	0	0
T12	2121	298	0	0
T13	4211	191	0	0
T14	4925	328	0	0
T16	0	0	0	2
T19	1842	20	0	0
T20	0	0	0	2
T21	0	0	0	2
T23	1147	58	0	0
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	3427	0	110
T10	2011	0	0	0
T11	1775	0	0	0
T13	4211	27	0	1
T14	4925	4	0	1
T16	1880	0	0	0
T18	1522	0	0	0
T24	1528	15	0	1
T25	0	45	0	1
T28	2534	0	0	0
T31	0	22	0	1
T35	1993	0	0	0
T46	0	3	0	1
T57	2727	0	0	0
T62	0	4	0	1
T63	0	4	0	1
T71	0	4	0	1
T72	0	4	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	85942	0	0
T4	663	352	0	0
T5	1093	287	0	0
T6	653	322	0	0
T8	0	194	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T37	0	7	0	0
T51	0	422	0	0
T52	920	0	0	0
T58	0	666	0	0
T59	0	1002	0	0
T60	0	292	0	0
T61	0	7	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	467844	0	294
T1	2668	1438	0	2
T2	1493	1430	0	2
T3	1841	294	0	0
T7	1778	27	0	0
T10	2011	337	0	0
T12	2121	298	0	0
T13	4211	191	0	0
T14	4925	328	0	0
T16	0	0	0	2
T19	1842	20	0	0
T20	0	0	0	2
T21	0	0	0	2
T23	1147	58	0	0
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	3333	0	97
T10	2011	0	0	0
T11	1775	0	0	0
T13	4211	61	0	1
T14	4925	73	0	1
T16	1880	0	0	0
T18	1522	0	0	0
T24	1528	0	0	0
T25	0	60	0	1
T27	0	3	0	1
T28	2534	0	0	0
T29	0	0	0	1
T35	1993	0	0	0
T45	0	7	0	1
T48	0	19	0	1
T57	2727	0	0	0
T63	0	4	0	0
T66	0	3	0	1
T67	0	3	0	1
T73	0	4	0	0
T74	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	85942	0	0
T4	663	352	0	0
T5	1093	287	0	0
T6	653	322	0	0
T8	0	194	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T37	0	7	0	0
T51	0	422	0	0
T52	920	0	0	0
T58	0	666	0	0
T59	0	1002	0	0
T60	0	292	0	0
T61	0	7	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	467844	0	294
T1	2668	1438	0	2
T2	1493	1430	0	2
T3	1841	294	0	0
T7	1778	27	0	0
T10	2011	337	0	0
T12	2121	298	0	0
T13	4211	191	0	0
T14	4925	328	0	0
T16	0	0	0	2
T19	1842	20	0	0
T20	0	0	0	2
T21	0	0	0	2
T23	1147	58	0	0
T52	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	3465	0	89
T4	663	0	0	0
T10	2011	0	0	0
T11	1775	0	0	0
T14	4925	3	0	1
T16	1880	0	0	0
T18	1522	0	0	0
T24	1528	0	0	0
T26	0	4	0	0
T27	0	3	0	1
T28	2534	0	0	0
T29	0	3	0	1
T32	0	12	0	1
T35	1993	0	0	0
T45	0	3	0	1
T57	2727	0	0	0
T66	0	3	0	1
T67	0	7	0	1
T75	0	3	0	1
T76	0	3	0	1
T77	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	209280204	0	0
T1	2668	2574	0	0
T2	1493	1432	0	0
T3	1841	1785	0	0
T7	1778	1683	0	0
T10	2011	1920	0	0
T12	2121	2069	0	0
T13	4211	4148	0	0
T14	4925	4830	0	0
T19	1842	1758	0	0
T23	1147	1090	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209386385	85942	0	0
T4	663	352	0	0
T5	1093	287	0	0
T6	653	322	0	0
T8	0	194	0	0
T17	3460	0	0	0
T25	2136	0	0	0
T26	1047	0	0	0
T37	0	7	0	0
T51	0	422	0	0
T52	920	0	0	0
T58	0	666	0	0
T59	0	1002	0	0
T60	0	292	0	0
T61	0	7	0	0
T62	2164	0	0	0
T63	2792	0	0	0
T64	2351	0	0	0