Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.67		66.67	100.00			72.34	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	209844151	9584751	0	0
boot_gen_cmd_rd_A	209844151	51941	0	0
boot_ins_cmd_rd_A	209844151	58254	0	0
ctrl_rd_A	209844151	50912	0	0
err_code_test_rd_A	209844151	57313	0	0
intr_enable_rd_A	209844151	56570	0	0
max_num_reqs_between_reseeds_rd_A	209844151	51351	0	0
regwen_rd_A	209844151	59901	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209844151	9584751	0	0
T20	107028	44144	0	0
T21	306230	125892	0	0
T22	0	572666	0	0
T46	3244	0	0	0
T47	2242	0	0	0
T48	2591	0	0	0
T49	2770	0	0	0
T50	1038	0	0	0
T51	776	0	0	0
T65	1579	0	0	0
T97	2250	0	0	0
T224	0	106412	0	0
T225	0	76019	0	0
T226	0	70608	0	0
T227	0	268215	0	0
T228	0	132802	0	0
T229	0	151072	0	0
T230	0	202999	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209844151	51941	0	0
T32	3996	0	0	0
T104	2692	0	0	0
T108	697	0	0	0
T111	8771	0	0	0
T224	305997	3329	0	0
T227	0	8205	0	0
T229	0	4358	0	0
T231	0	2767	0	0
T232	0	1971	0	0
T233	0	5194	0	0
T234	0	1645	0	0
T235	0	2029	0	0
T236	0	5728	0	0
T237	0	5046	0	0
T238	1071	0	0	0
T239	2305	0	0	0
T240	6760	0	0	0
T241	2093	0	0	0
T242	1745	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209844151	58254	0	0
T32	3996	0	0	0
T104	2692	0	0	0
T108	697	0	0	0
T111	8771	0	0	0
T224	305997	3979	0	0
T227	0	8883	0	0
T229	0	4986	0	0
T231	0	3191	0	0
T232	0	2123	0	0
T233	0	5682	0	0
T234	0	1722	0	0
T235	0	2337	0	0
T236	0	6601	0	0
T237	0	5853	0	0
T238	1071	0	0	0
T239	2305	0	0	0
T240	6760	0	0	0
T241	2093	0	0	0
T242	1745	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209844151	50912	0	0
T36	40902	2	0	0
T43	0	4	0	0
T59	1653	0	0	0
T60	568	0	0	0
T66	2364	0	0	0
T67	1498	0	0	0
T73	2681	0	0	0
T100	2172	0	0	0
T105	2318	0	0	0
T143	0	2	0	0
T224	0	3481	0	0
T227	0	8151	0	0
T229	0	4400	0	0
T243	0	6	0	0
T244	0	7	0	0
T245	0	5	0	0
T246	0	1	0	0
T247	1311	0	0	0
T248	1765	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209844151	57313	0	0
T32	3996	0	0	0
T104	2692	0	0	0
T108	697	0	0	0
T111	8771	0	0	0
T224	305997	3586	0	0
T227	0	8831	0	0
T229	0	5057	0	0
T231	0	3196	0	0
T232	0	2103	0	0
T233	0	5881	0	0
T234	0	1831	0	0
T235	0	2327	0	0
T236	0	6312	0	0
T237	0	5320	0	0
T238	1071	0	0	0
T239	2305	0	0	0
T240	6760	0	0	0
T241	2093	0	0	0
T242	1745	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209844151	56570	0	0
T36	40902	43	0	0
T59	1653	0	0	0
T60	568	0	0	0
T66	2364	0	0	0
T67	1498	0	0	0
T73	2681	0	0	0
T100	2172	0	0	0
T105	2318	0	0	0
T224	0	3368	0	0
T227	0	8166	0	0
T229	0	4960	0	0
T231	0	3114	0	0
T232	0	2479	0	0
T233	0	5263	0	0
T243	0	27	0	0
T244	0	52	0	0
T247	1311	0	0	0
T248	1765	0	0	0
T249	0	22	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209844151	51351	0	0
T32	3996	0	0	0
T104	2692	0	0	0
T108	697	0	0	0
T111	8771	0	0	0
T224	305997	3375	0	0
T227	0	8043	0	0
T229	0	4202	0	0
T231	0	2986	0	0
T232	0	1965	0	0
T233	0	4986	0	0
T234	0	1519	0	0
T235	0	2168	0	0
T236	0	5489	0	0
T237	0	5138	0	0
T238	1071	0	0	0
T239	2305	0	0	0
T240	6760	0	0	0
T241	2093	0	0	0
T242	1745	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209844151	59901	0	0
T32	3996	0	0	0
T104	2692	0	0	0
T108	697	0	0	0
T111	8771	0	0	0
T224	305997	3634	0	0
T227	0	9277	0	0
T229	0	5398	0	0
T231	0	3387	0	0
T232	0	2358	0	0
T233	0	5816	0	0
T234	0	1812	0	0
T235	0	2582	0	0
T236	0	6731	0	0
T237	0	5746	0	0
T238	1071	0	0	0
T239	2305	0	0	0
T240	6760	0	0	0
T241	2093	0	0	0
T242	1745	0	0	0